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r01ds0062ej0120 rev.1.20 page 1 of 99 sep 26, 2011 r32c/111 group renesas mcu r01ds0062ej0120 rev.1.20 sep 26, 2011 datasheet r32c/111 group datasheet 1. overview 1.1 features the m16c family offers a robust platform of 32-/16 -bit cisc microcomputers (mcus) featuring high rom code efficiency, extensive emi/ems noise immunity, ultra-low power consumption, high-speed processing in actual applications, an d numerous and varied in tegrated perip herals. extensive dev ice scalability from low- to high-end, featuring a single architecture as well as compatible pin assignments and peripheral functions, provides support for a vast range of application fields. the r32c/100 series is a high-end microcontroller se ries in the m16c family. with a 4-gbyte memory space, it achieves maximum code efficiency and high-speed processing with 32-bit cisc architecture, multiplier, multiply-accumulate unit, and floating point unit. the selecti on from the broadest choice of on- chip peripheral devices ? uart, crc, dmac, a/d and d/a converters, timers, i 2 c, and watchdog timer enables to minimize external components. the r32c/100 series, in particular, provides t he r32c/111 group as a standard product. this product, provided as 100-pin plastic mol ded lga, and 100-/80-/64-pin plasti c molded lqfp package, has a maximum of nine channels of serial interface. 1.1.1 applications audio, cameras, television, home appliance, printer, meter, office/industrial equipment, communication/ portable devices
r01ds0062ej0120 rev.1.20 page 2 of 99 sep 26, 2011 r32c/111 group 1. overview 1.1.2 performance overview table 1.1 to table 1.6 show the performance overview of the r32c/111 group. note: 1. contact a renesas electronics sales office to use the optional features. table 1.1 performance overview for the 100-pin package (1/2) unit function explanation cpu central processing unit r32c/100 series cpu core ? basic instructions: 108 ? minimum instruction execution time: 20 ns (f(cpu) = 50 mhz) ? multiplier: 32-bit 32-bit 64-bit ? multiply-accumulate unit: 32-bit 32-bit + 64-bit 64-bit ? ieee-754 compatible fpu: single precision ? 32-bit barrel shifter ? operating mode: single-chip mode, memory expansion mode, microprocessor mode (optional (1) ) memory flash memory: 256 to 512 kbytes ram: 32 to 63 kbytes data flash: 4 kbytes 2 blocks refer to table 1.7 for memory size of each product group voltage detector low voltage detector optional (1) low voltage detection interrupt clock clock generator ? 4 circuits (main clo ck, sub clock, pll, on-chip oscillator) ? oscillation stop detector: main cloc k oscillator stop/restart detection ? frequency divide circuit: divide-by-2 to divide-by-24 selectable ? low power modes: wait mode, stop mode external bus expansion bus and memory expansion ? address space: 4 gbytes (of which up to 64 mbytes is user accessible) ? external bus interface: support for wa it-state insertion, 4 chip select outputs, 3v/5v interface ? bus format: separate bus/multiplexed bus sele ctable, data bus width selectable (8/16 bits) interrupts interrupt vectors: 261 external interrupt inputs: nmi , int 6, key input 4 interrupt priority levels: 7 watchdog timer 15 bits 1 (selectable input frequency from prescaler output) dma dmac 4 channels ? cycle-steal transfer mode ? request sources: 51 ? 2 transfer modes: single transfer, repeat transfer dmac ii ? can be activated by any peripheral interrupt source ? 3 transfer functions: immediate da ta transfer, calculation transfer, chained transfer i/o ports programmable i/o ports ? 2 input-only ports ? 82 cmos i/o ports ? 2 n-channel open drain ports ? a pull-up resistor is selectable for every 4 input ports
r01ds0062ej0120 rev.1.20 page 3 of 99 sep 26, 2011 r32c/111 group 1. overview note: 1. contact a renesas electronics sales office to use the optional features. table 1.2 performance overview for the 100-pin package (2/2) unit function explanation timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse-width modulation (pwm) mode two-phase pulse signal processing in event counter mode (two- phase encoder input) 3 timer b 16-bit timer 6 timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode three-phase motor control timer three-phase motor control timer 1 (timers a1, a2, a4, and b2 used) 8-bit programmable dead time timer serial interface uart0 to uart8 asynchronous/synchronous serial interface 9 channels ?i 2 c-bus (uart0 to uart6) ? special mode 2 (uart0 to uart6) ? iebus (optional (1) ) (uart0 to uart6) a/d converter 10-bit resolution 26 channels sample and hold functionality integrated d/a converter 8-bit resolution 2 crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1) x-y converter 16 bits 16 bits intelligent i/o time measurement (input capture): 16 bits 16 waveform generation (output compare): 16 bits 19 serial interface: variable-length synchronous serial i/o mode, iebus mode (optional (1) ) flash memory programming and erasure supply voltage: vcc1 = vcc2 = 3.0 to 5.5 v minimum endurance: 1,000 program/erase cycles security protection: rom code protect, id code protect debugging: on-chip debug, on-board flash programming operating frequency/supply voltage 50 mhz/vcc1 = 3.0 to 5.5 v, vcc2 = 3.0 v to vcc1 operating temperature -20c to 85c (n version) -40c to 85c (d version) current consumption 32 ma (vcc1 = vcc2 = 5.0 v, f(cpu) = 50 mhz) 8 a (vcc1 = vcc2 = 3.3 v, f(xcin) = 32.768 khz, in wait mode) package 100-pin plastic molded lqfp (plqp0100kb-a) 100-pin plastic molded tflga (ptlg0100ka-a)
r01ds0062ej0120 rev.1.20 page 4 of 99 sep 26, 2011 r32c/111 group 1. overview note: 1. contact a renesas electronics sales office to use the optional features. table 1.3 performance overview for the 80-pin package (1/2) unit function explanation cpu central processing unit r32c/100 series cpu core ? basic instructions: 108 ? minimum instruction execution time: 20 ns (f(cpu) = 50 mhz) ? multiplier: 32-bit 32-bit 64-bit ? multiply-accumulate unit: 32-bit 32-bit + 64-bit 64-bit ? ieee-754 compatible fpu: single precision ? 32-bit barrel shifter ? operating mode: single-chip mode memory flash memory: 128/256 kbytes ram: 32 kbytes data flash: 4 kbytes 2 blocks refer to table 1.7 for memory size of each product group voltage detector low voltage detector optional (1) low voltage detection interrupt clock clock generator ? 4 circuits (main clo ck, sub clock, pll, on-chip oscillator) ? oscillation stop detector: main cloc k oscillator stop/restart detection ? frequency divide circuit: divide-by-2 to divide-by-24 selectable ? low power modes: wait mode, stop mode interrupts interrupt vectors: 261 external interrupt inputs: nmi , int 6, key input 4 interrupt priority levels: 7 watchdog timer 15 bits 1 (selectable input frequency from prescaler output) dma dmac 4 channels ? cycle-steal transfer mode ? request sources: 47 ? 2 transfer modes: single transfer, repeat transfer dmac ii ? can be activated by any peripheral interrupt source ? 3 transfer functions: immediate da ta transfer, calculation transfer, chained transfer i/o ports programmable i/o ports ? 1 input-only port ? 65 cmos i/o ports ? 2 n-channel open drain ports ? a pull-up resistor is selectable for every 4 input ports
r01ds0062ej0120 rev.1.20 page 5 of 99 sep 26, 2011 r32c/111 group 1. overview notes: 1. timer b4 is available in timer mode only. 2. contact a renesas electronics sales office to use the optional features. table 1.4 performance overview for the 80-pin package (2/2) unit function explanation timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse-width modulation (pwm) mode two-phase pulse signal processing in event counter mode (two- phase encoder input) 3 timer b 16-bit timer 6 (1) timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode three-phase motor control timer three-phase motor control timer 1 (timers a1, a2, a4, and b2 used) 8-bit programmable dead time timer serial interface uart0 to uart5, uart8 asynchronous/synchronous serial interface 7 channels ?i 2 c-bus (uart0 to uart5) ? special mode 2 (uart0 to uart3, uart5) ? iebus (optional (2) ) (uart0 to uart5) a/d converter 10-bit resolution 26 channels sample and hold functionality integrated d/a converter 8-bit resolution 1 crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1) x-y converter 16 bits 16 bits intelligent i/o time measurement (input capture): 16 bits 16 waveform generation (output compare): 16 bits 19 serial interface: variable-length synchronous serial i/o mode, iebus mode (optional (2) ) flash memory programming and erasure s upply voltage: vcc1 = 3.0 to 5.5 v minimum endurance: 1,000 program/erase cycles security protection: rom code protect, id code protect debugging: on-chip debug, on-board flash programming operating frequency/supply voltage 50 mhz/vcc1 = 3.0 to 5.5 v operating temperature -20c to 85c (n version) -40c to 85c (d version) current consumption 32 ma (vcc1 = 5.0 v, f(cpu) = 50 mhz) 8 a (vcc1 = 3.3 v, f(xcin) = 32.768 khz, in wait mode) package 80-pin plastic molded lqfp (plqp0080kb-a)
r01ds0062ej0120 rev.1.20 page 6 of 99 sep 26, 2011 r32c/111 group 1. overview note: 1. contact a renesas electronics sales office to use the optional features. table 1.5 performance overview for the 64-pin package (1/2) unit function explanation cpu central processing unit r32c/100 series cpu core ? basic instructions: 108 ? minimum instruction execution time: 20 ns (f(cpu) = 50 mhz) ? multiplier: 32-bit 32-bit 64-bit ? multiply-accumulate unit: 32-bit 32-bit + 64-bit 64-bit ? ieee-754 compatible fpu: single precision ? 32-bit barrel shifter ? operating mode: single-chip mode memory flash memory: 128/256 kbytes ram: 32 kbytes data flash: 4 kbytes 2 blocks refer to table 1.7 for memory size of each product group voltage detector low voltage detector optional (1) low voltage detection interrupt clock clock generator ? 4 circuits (main clo ck, sub clock, pll, on-chip oscillator) ? oscillation stop detector: main cloc k oscillator stop/restart detection ? frequency divide circuit: divide-by-2 to divide-by-24 selectable ? low power modes: wait mode, stop mode interrupts interrupt vectors: 261 external interrupt inputs: nmi , int 6, key input 4 interrupt priority levels: 7 watchdog timer 15 bits 1 (selectable input frequency from prescaler output) dma dmac 4 channels ? cycle-steal transfer mode ? request sources: 45 ? 2 transfer modes: single transfer, repeat transfer dmac ii ? can be activated by any peripheral interrupt source ? 3 transfer functions: immediate da ta transfer, calculation transfer, chained transfer i/o ports programmable i/o ports ? 1 input-only port ? 49 cmos i/o ports ? 2 n-channel open drain ports ? a pull-up resistor is selectable for every 4 input ports
r01ds0062ej0120 rev.1.20 page 7 of 99 sep 26, 2011 r32c/111 group 1. overview notes: 1. timer b4 is available in timer mode only. 2. contact a renesas electronics sales office to use the optional features. table 1.6 performance overview for the 64-pin package (2/2) unit function explanation timer timer a 16-bit timer 5 timer mode, event counter mode, one-shot timer mode, pulse-width modulation (pwm) mode two-phase pulse signal processing in event counter mode (two- phase encoder input) 3 timer b 16-bit timer 6 (1) timer mode, event counter mode, pulse frequency measurement mode, pulse-width measurement mode three-phase motor control timer three-phase motor control timer 1 (timers a1, a2, a4, and b2 used) 8-bit programmable dead time timer serial interface uart0 to uart3, uart5, uart8 asynchronous/synchronous serial interface 6 channels ?i 2 c-bus (uart0 to uart3, uart5) ? special mode 2 (uart0 to uart3, uart5) ? iebus (optional (2) ) (uart0 to uart3, uart5) a/d converter 10-bit resolution 20 channels sample and hold functionality integrated d/a converter 8-bit resolution 1 crc calculator crc-ccitt (x 16 + x 12 + x 5 + 1) x-y converter 16 bits 16 bits intelligent i/o time measurement (input capture): 16 bits 16 waveform generation (output compare): 16 bits 19 serial interface: variable-length synchronous serial i/o mode, iebus mode (optional (2) ) flash memory programming and erasure s upply voltage: vcc1 = 3.0 to 5.5 v minimum endurance: 1,000 program/erase cycles security protection: rom code protect, id code protect debugging: on-chip debug, on-board flash programming operating frequency/supply voltage 50 mhz/vcc1 = 3.0 to 5.5 v operating temperature -20c to 85c (n version) -40c to 85c (d version) current consumption 32 ma (vcc1 = 5.0 v, f(cpu) = 50 mhz) 8 a (vcc1 = 3.3 v, f(xcin) = 32.768 khz, in wait mode) package 64-pin plastic molded lqfp (plqp0064kb-a)
r01ds0062ej0120 rev.1.20 page 8 of 99 sep 26, 2011 r32c/111 group 1. overview 1.2 product information table 1.7 lists the product information and figu re 1.1 shows the details of the part number. notes: 1. the old package codes are as follows: plqp0100kb-a: 100p6q-a ptlg0100ka-a: 100f0m plqp0080kb-a: 80p6q-a plqp0064kb-a: 64p6q-a 2. data flash memory provides an additional 8 kbytes of rom. table 1.7 r32c/111 group product list as of september, 2011 part number package code (1) rom capacity (2) ram capacity remarks r5f64110nfb (p) plqp0100kb-a 256 kbytes +8 kbytes 63 kbytes -20c to 85c (n version) r5f64110dfb -40c to 85c (d version) r5f64111nfb (p) 384 kbytes +8 kbytes -20c to 85c (n version) r5f64111dfb -40c to 85c (d version) r5f64112nfb (p) 512 kbytes +8 kbytes -20c to 85c (n version) r5f64112dfb -40c to 85c (d version) r5f64114nfb (p) 256 kbytes +8 kbytes 40 kbytes -20c to 85c (n version) r5f64114dfb -40c to 85c (d version) r5f64115nfb (p) 384 kbytes +8 kbytes -20c to 85c (n version) r5f64115dfb -40c to 85c (d version) r5f64116nfb (p) 512 kbytes +8 kbytes -20c to 85c (n version) r5f64116dfb -40c to 85c (d version) r5f64111nlg ptlg0100ka-a 384 kbytes +8 kbytes 63 kbytes -20c to 85c (n version) r5f64111dlg (p) -40c to 85c (d version) r5f64112nlg 512 kbytes +8 kbytes -20c to 85c (n version) r5f64112dlg (p) -40c to 85c (d version) r5f6411fnlg 256 kbytes +8 kbytes 32 kbytes -20c to 85c (n version) r5f6411fdlg (p) -40c to 85c (d version) r5f6411enfp (p) plqp080kb-a 128 kbytes +8 kbytes 32 kbytes -20c to 85c (n version) r5f6411edfp (p) -40c to 85c (d version) r5f6411fnfp (p) 256 kbytes +8 kbytes -20c to 85c (n version) r5f6411fdfp (p) -40c to 85c (d version) r5f6411enfn (p) plqp064kb-a 128 kbytes +8 kbytes 32 kbytes -20c to 85c (n version) r5f6411edfn -40c to 85c (d version) r5f6411fnfn (p) 256 kbytes +8 kbytes -20c to 85c (n version) r5f6411fdfn -40c to 85c (d version) (p): on planning phase
r01ds0062ej0120 rev.1.20 page 9 of 99 sep 26, 2011 r32c/111 group 1. overview figure 1.1 part numbering part number r5 f 64 11 6 n xxx fb package code fb : plqp0100kb-a fp : plqp0080kb-a fn : plqp0064kb-a lg : ptlg0100ka-a rom number omitted in the flash memory version memory type f : flash memory version r32c/111 group r32c/100 series rom/ram capacity 0 : 256 kb/63 kb 1 : 384 kb/63 kb 2 : 512 kb/63 kb 4 : 256 kb/40 kb 5 : 384 kb/40 kb 6 : 512 kb/40 kb e : 128 kb/32 kb f : 256 kb/32 kb temperature code n : -20c to 85c d : -40c to 85c
r01ds0062ej0120 rev.1.20 page 10 of 99 sep 26, 2011 r32c/111 group 1. overview 1.3 block diagram figure 1.2 to figure 1.4 show block diagram of the r32c/111 group. figure 1.2 r32c/111 group block diagram for the 100-pin package port p0 port p1 port p2 port p3 port p4 port p5 port p6 8 8 8 8 8 8 8 port p7 p8_5 port p9 port p10 8 7 5 8 vcc2 vcc1 port p8 vcc1 p9_1 x-y converter: 16 bits 16 bits crc calculator (ccitt) x 16 + x 12 + x 5 + 1 watchdog timer: 15 bits r32c/100 series cpu core r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb flg intb isp usp pc svf svp vct memory rom ram multiplier floating-point unit r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb d/a converter: 8 bits 2 channels a/d converter: 10 bits 1 circuit standard: 10 inputs maximum: 26 inputs timer: timer a 16 bits 5 timers timer b 16 bits 6 timers three-phase motor controller serial interface: 9 channels intelligent i/o time measurement: 16 wave generation: 19 serial interface: - variable-length synchronous serial i/o - iebus clock generator: 4 circuits - xin-xout - xcin-xcout - on-chip oscillator - pll frequency synthesizer dmac dmac ii peripheral functions
r01ds0062ej0120 rev.1.20 page 11 of 99 sep 26, 2011 r32c/111 group 1. overview figure 1.3 r32c/111 group block diagram for the 80-pin package port p0 port p1 port p2 port p3 port p6 8 8 8 8 8 p8_5 port p9 port p10 7 4 8 peripheral functions port p8 clock generator: 4 circuits - xin-xout - xcin-xcout - on-chip oscillator - pll frequency synthesizer x-y converter: 16 bits 16 bits crc calculator (ccitt) x 16 + x 12 + x 5 + 1 watchdog timer: 15 bits dmac dmac ii r32c/100 series cpu core r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb flg intb isp usp pc svf svp vct memory rom ram multiplier floating-point unit r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb d/a converter: 8 bits 1 channel a/d converter: 10 bits 1 circuit standard: 10 inputs maximum: 26 inputs timer: timer a 16 bits 5 timers timer b 16 bits 6 timers three-phase motor controller serial interface: 7 channels intelligent i/o time measurement: 16 wave generation: 19 serial interface: - variable-length synchronous serial i/o - iebus port p7 8
r01ds0062ej0120 rev.1.20 page 12 of 99 sep 26, 2011 r32c/111 group 1. overview figure 1.4 r32c/111 group block diagram for the 64-pin package port p0 port p1 port p2 port p3 port p7 4 3 8 4 8 p8_5 port p10 7 8 peripheral functions port p8 p9_3 clock generator: 4 circuits - xin-xout - xcin-xcout - on-chip oscillator - pll frequency synthesizer x-y converter: 16 bits 16 bits crc calculator (ccitt) x 16 + x 12 + x 5 + 1 watchdog timer: 15 bits dmac dmac ii r32c/100 series cpu core r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb flg intb isp usp pc svf svp vct memory rom ram multiplier floating-point unit r2r0 r3r1 r6r4 r7r5 a0 a1 a2 a3 fb sb d/a converter: 8 bits 1 channel a/d converter: 10 bits 1 circuit standard: 8 inputs maximum: 20 inputs timer: timer a 16 bits 5 timers timer b 16 bits 6 timers three-phase motor controller serial interface: 6 channels intelligent i/o time measurement: 16 wave generation: 19 serial interface: - variable-length synchronous serial i/o - iebus port p6 8
r01ds0062ej0120 rev.1.20 page 13 of 99 sep 26, 2011 r32c/111 group 1. overview 1.4 pin assignments figure 1.5 to figure 1.8 show the pin assignments (top view) and table 1.8 to t able 1.14 show the pin characteristics. figure 1.5 pin assignment for the 100-pin package (top view) 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 100 99 98 97 96 95 94 93 92 91 90 89 87 86 85 84 83 82 81 80 79 78 77 76 75 74 88 73 rxd4 / scl4 / stxd4 / adtrg / p9_7 p7_0 / ta0out / txd2 / sda2 / srxd2 / iio1_6 / outc2_0 / istxd2 / ieout (note 2) p6_7 / txd1 / sda1 / srxd1 avcc vref an_0 / p10_0 avss an_1 / p10_1 an_2 / p10_2 an_3 / p10_3 ki0 / an_4 / p10_4 ki1 / an_5 / p10_5 ki2 / an_6 / p10_6 ki3 / an_7 / p10_7 an0_0 / d0 / p0_0 an0_1 / d1 / p0_1 an0_2 / d2 / p0_2 an0_3 / d3 / p0_3 an0_4 / d4 / p0_4 an0_5 / d5 / p0_5 an0_6 / d6 / p0_6 an0_7 / d7 / p0_7 p6_6 / rxd1 / scl1 / stxd1 p6_5 / clk1 p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 p6_3 / txd0 / sda0 / srxd0 p6_2 / tb2in / rxd0 / scl0 / stxd0 p6_1 / tb1in / clk0 p6_0 / tb0in / cts0 / rts0 / ss0 p5_7 / rdy / cs3 / cts7 / rts7 p5_6 / ale / cs2 / rxd7 p5_5 / hold / clk7 p5_4 / hlda / cs1 / txd7 p5_3 / clkout / bclk p5_2 / rd p5_1 / wr1 / bc1 p5_0 / wr0 / wr p4_7 / cs0 / a23 / txd6 / sda6 / srxd6 p4_6 / cs1 / a22 / rxd6 / scl6 / stxd6 p4_5 / cs2 / a21 / clk6 p4_4 / cs3 / a20 / cts6 / rts6 / ss6 txd4 / sda4 / srxd4 / anex1 / p9_6 clk4 / anex0 / p9_5 cts4 / rts4 / ss4 / tb4in / da1 / p9_4 vdc0 p9_1 vdc1 nsd cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc1 nmi / p8_5 int2 / p8_4 int1 / p8_3 int0 / p8_2 iio1_5 / ud0b / ud1b / cts5 / rts5 / ss5 / u / ta4in / p8_1 ud0a / ud1a / rxd5 / scl5 / stxd5 / u / ta4out / p8_0 iio1_4 / ud0b / ud1b / clk5 / ta3in / p7_7 iio1_3 / ud0a / ud1a / txd5 / sda5 / srxd5 / cts8 / rts8 / ta3out / p7_6 iio1_2 / rxd8 / w / ta2in / p7_5 iio1_1 / clk8 / w / ta2out / p7_4 iio1_0 / cts2 / rts2 / ss2 / txd8 / v / ta1in / p7_3 p7_2 / ta1out / v / clk2 p7_1 / ta0in / tb5in / rxd2 / scl2 / stxd2 / iio1_7 / outc2_2 / isrxd2 / iein tb3in / da0 / p9_3 iio0_1 / iio1_1 / d9 / p1_1 iio0_2 / iio1_2 / d10 / p1_2 p1_3 / d11 / iio0_3 / iio1_3 p1_4 / d12 / iio0_4 / iio1_4 p1_5 / d13 / int3 / iio0_5 / iio1_5 p1_6 / d14 / int4 / iio0_6 / iio1_6 p1_7 / d15 / int5 / iio0_7 / iio1_7 p2_0 / a0 / [a0/d0] / bc0 / [bc0/d0] / an2_0 vss p3_0 / a8 / [a8/d8] / ta0out / ud0a / ud1a vcc2 p3_1 / a9 / [a9/d9] / ta3out / ud0b / ud1b p3_2 / a10 / [a10/d10] / ta1out / v p3_3 / a11 / [a11/d11] / ta1in / v p3_4 / a12 / [a12/d12] / ta2out / w p3_5 / a13 / [a13/d13] / ta2in / w p3_6 / a14 / [a14/d14] / ta4out / u p3_7 / a15 / [a15/d15] / ta4in / u p4_0 / a16 / cts3 / rts3 / ss3 p4_1 / a17 / clk3 p4_2 / a18 / rxd3 / scl3 / stxd3 / isrxd2 / iein p4_3 / a19 / txd3 / sda3 / srxd3 / outc2_0 / istxd2 / ieout p2_1 / a1 / [a1/d1] / an2_1 p2_2 / a2 / [a2/d2] / an2_2 p2_3 / a3 / [a3/d3] / an2_3 p2_4 / a4 / [a4/d4] / an2_4 p2_5 / a5 / [a5/d5] / an2_5 p2_6 / a6 / [a6/d6] / an2_6 p2_7 / a7 / [a7/d7] / an2_7 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 iio0_0 / iio1_0 / d8 / p1_0 plqp0100kb-a (100p6q-a) (top view) r32c/111 group (note 1) (note 3) notes: 1. pin names in brackets [ ] represent a functional signal as a whole and should not be considered as two separate pins. 2. pins p7_0 and p7_1 are open drain outputs. 3. the position of pin number 1 varies by product. refer to the index mark in attached ?package dimensions?. vcc1 vcc2 (note 2)
r01ds0062ej0120 rev.1.20 page 14 of 99 sep 26, 2011 r32c/111 group 1. overview figure 1.6 pin assignment for the 100-pin lga package (top view) p1_3 ptlg0100ka-a (100f0m) (top view) r32c/111 group (note 2) vcc1 vcc2 p1_2 p0_7 p0_3 p10_6 p10_4 p10_1 vref p9_5 p9_4 p1_4 p1_5 / int3 p0_6 p0_4 p0_2 p10_5 p10_2 avcc p9_6 vdc0 p2_0 p1_7 / int5 p1_1 p1_0 p0_1 p10_3 avss p9_7 vdc1 nsd p2_2 p2_1 p2_3 p2_4 p0_5 p10_7 p10_0 p9_1 cnvss p8_7 / xcin p2_6 p2_7 vss p2_5 p1_6 / int4 p0_0 p9_3 p8_6 / xcout reset xout p3_0 vcc2 p3_1 p3_4 p3_5 p8_4 / int2 p8_1 vss xin vcc1 p3_2 p3_3 p4_4 p4_7 p5_7 p6_5 p7_6 p8_3 / int1 p8_5 / nmi p8_2 / int0 p3_6 p3_7 p4_5 p5_3 p5_6 p6_2 p6_7 p7_5 p7_7 p8_0 p7_0 (note 1) p4_1 p4_0 p4_6 p5_2 p5_5 p6_1 p6_4 p7_3 p7_4 p4_2 p4_3 p5_0 p5_1 p5_4 p6_0 p6_3 p6_6 p7_1 (note 1) p7_2 k j h g f e d c b a 10987654321 vcc1 vcc2 k j h g f e d c b a 10987654321 notes: 1. pins p7_0 and p7_1 are open drain outputs. 2. the pin position a1 varies by product. refer to the index mark in attached ?package dimensions?.
r01ds0062ej0120 rev.1.20 page 15 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.8 pin characteristics for the 100-pin package (1/3) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin analog pin bus control pin qfp lga 1 a1 p9_4 tb4in cts4 / rts4 / ss4 da1 2 e4 p9_3 tb3in da0 3b1vdc0 4 d3 p9_1 5c2vdc1 6c1nsd 7 d2 cnvss 8 d1 xcin p8_7 9 e3 xcout p8_6 10 e2 reset 11 e1 xout 12 f3 vss 13 f2 xin 14 f1 vcc1 15 g2 p8_5 nmi 16 f5 p8_4 int2 17 g3 p8_3 int1 18 g1 p8_2 int0 19 f4 p8_1 ta4in/ ucts5 / rts5 / ss5 iio1_5/ud0b/ud1b 20 h1 p8_0 ta4out/u rxd5/scl5/stxd5 ud0a/ud1a 21 h2 p7_7 ta3in clk5 iio1_4/ud0b/ud1b 22 g4 p7_6 ta3out txd5/sda5/ srxd5/ cts8 / rts8 iio1_3/ud0a/ud1a 23 h3 p7_5 ta2in/ w rxd8 iio1_2 24 j1 p7_4 ta2out/w clk8 iio1_1 25 j2 p7_3 ta1in/ vcts2 / rts2 / ss2 / txd8 iio1_0 26 k1 p7_2 ta1out/v clk2 27 k2 p7_1 ta0in/ tb5in rxd2/scl2/stxd2 iio1_7/outc2_2/ isrxd2/iein 28 j3 p7_0 ta0out txd2/sda2/srxd2 iio1_6/outc2_0/ istxd2/ieout 29 h4 p6_7 txd1/sda1/srxd1 30 k3 p6_6 rxd1/scl1/stxd1 31 g5 p6_5 clk1 32 j4 p6_4 cts1 / rts1 / ss1 outc2_1/isclk2 33 k4 p6_3 txd0/sda0/srxd0 34 h5 p6_2 tb2in rxd0/scl0/stxd0 35 j5 p6_1 tb1in clk0 36 k5 p6_0 tb0in cts0 / rts0 / ss0 37 g6 p5_7 cts7 / rts7 rdy / cs3 38 h6 p5_6 rxd7 ale/ cs2 39 j6 p5_5 clk7 hold
r01ds0062ej0120 rev.1.20 page 16 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.9 pin characteristics for the 100-pin package (2/3) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin analog pin bus control pin qfp lga 40 k6 p5_4 txd7 hlda / cs1 41 h7 p5_3 clkout/ bclk 42 j7 p5_2 rd 43 k7 p5_1 wr1 / bc1 44 k8 p5_0 wr0 / wr 45 g7 p4_7 txd6/sda6/srxd6 cs0 /a23 46 j8 p4_6 rxd6/scl6/stxd6 cs1 /a22 47 h8 p4_5 clk6 cs2 /a21 48 g8 p4_4 cts6 / rts6 / ss6 cs3 /a20 49 k9 p4_3 txd3/sda3/srxd3 outc2_0/istxd2/ ieout a19 50 k10 p4_2 rxd3/scl3/stxd3 isrxd2/iein a18 51 j10 p4_1 clk3 a17 52 j9 p4_0 cts3 / rts3 / ss3 a16 53 h9 p3_7 ta4in/ u a15(/d15) 54 h10 p3_6 ta4out/u a14(/d14) 55 f6 p3_5 ta2in/ w a13(/d13) 56 f7 p3_4 ta2out/w a12(/d12) 57 g9 p3_3 ta1in/ v a11(/d11) 58 g10 p3_2 ta1out/v a10(/d10) 59 f8 p3_1 ta3out ud0b/ud1b a9(/d9) 60 f9 vcc2 61 f10 p3_0 ta0out ud0a/ud1a a8(/d8) 62 e8 vss 63 e9 p2_7 an2_7 a7(/d7) 64 e10 p2_6 an2_6 a6(/d6) 65 e7 p2_5 an2_5 a5(/d5) 66 d7 p2_4 an2_4 a4(/d4) 67 d8 p2_3 an2_3 a3(/d3) 68 d10 p2_2 an2_2 a2(/d2) 69 d9 p2_1 an2_1 a1(/d1) 70 c10 p2_0 an2_0 a0(/d0)/ bc0 (/d0) 71 c9 p1_7 int5 iio0_7/iio1_7 d15 72 e6 p1_6 int4 iio0_6/iio1_6 d14 73 b9 p1_5 int3 iio0_5/iio1_5 d13 74 b10 p1_4 iio0_4/iio1_4 d12 75 a10 p1_3 iio0_3/iio1_3 d11 76 a9 p1_2 iio0_2/iio1_2 d10 77 c8 p1_1 iio0_1/iio1_1 d9 78 c7 p1_0 iio0_0/iio1_0 d8 79 a8 p0_7 an0_7 d7
r01ds0062ej0120 rev.1.20 page 17 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.10 pin characteristics for the 100-pin package (3/3) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin analog pin bus control pin qfp lga 80 b8 p0_6 an0_6 d6 81 d6 p0_5 an0_5 d5 82 b7 p0_4 an0_4 d4 83 a7 p0_3 an0_3 d3 84 b6 p0_2 an0_2 d2 85 c6 p0_1 an0_1 d1 86 e5 p0_0 an0_0 d0 87 d5 p10_7 ki3 an_7 88 a6 p10_6 ki2 an_6 89 b5 p10_5 ki1 an_5 90 a5 p10_4 ki0 an_4 91 c5 p10_3 an_3 92 b4 p10_2 an_2 93 a4 p10_1 an_1 94 c4 avss 95 d4 p10_0 an_0 96 a3 vref 97 b3 avcc 98 c3 p9_7 rxd4/scl4/stxd4 adtrg 99 b2 p9_6 txd4/sda4/srxd4 anex1 100 a2 p9_5 clk4 anex0
r01ds0062ej0120 rev.1.20 page 18 of 99 sep 26, 2011 r32c/111 group 1. overview figure 1.7 pin assignment for the 80-pin package (top view) 21 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 27 28 29 30 31 32 80 79 78 77 76 75 74 73 72 71 70 69 67 66 65 64 63 62 61 68 an_1 / p10_1 p7_6 / ta3out / txd5 / sda5 / srxd5 / cts8 / rts8 / iio1_3 / ud0a / ud1a p7_5 / ta2in / w / rxd8 / iio1_2 avcc vref avss an_2 / p10_2 an_3 / p10_3 ki0 / an_4 / p10_4 ki1 / an_5 / p10_5 ki2 / an_6 / p10_6 ki3 / an_7 / p10_7 an0_0 / p0_0 an0_1 / p0_1 p7_4 / ta2out / w / clk8 / iio1_1 p7_3 / ta1in / v / cts2 / rts2 / ss2 / txd8 / iio1_0 p7_2 / ta1out / v / clk2 p7_1 / ta0in / tb5in / rxd2 / scl2 / stxd2 / iio1_7 / outc2_2 / isrxd2 / iein p7_0 / ta0out / txd2 / sda2 / srxd2 / iio1_6 / outc2_0 / istxd2 / ieout (note 1) p6_7 / txd1 / sda1 / srxd1 p6_6 / rxd1 / scl1 / stxd1 p6_5 / clk1 p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 p3_7 / ta4in / u p3_6 / ta4out / u p3_5 / ta2in / w p3_4 / ta2out / w an_0 / p10_0 rxd4 / scl4 / stxd4 / adtrg / p9_7 txd4 / sda4 / srxd4 / anex1 / p9_6 tb3in / da0 / p9_3 vdc0 vdc1 nsd cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc1 nmi / p8_5 int2 / p8_4 int1 / p8_3 int0 / p8_2 iio1_5 / ud0b / ud1b / cts5 / rts5 / ss5 / u / ta4in / p8_1 ud0a / ud1a / rxd5 / scl5 / stxd5 / u / ta4out / p8_0 iio1_4 / ud0b / ud1b / clk5 / ta3in / p7_7 clk4 / anex0 / p9_5 an0_3 / p0_3 an0_4 / p0_4 an0_5 / p0_5 an0_6 / p0_6 p0_7 / an0_7 p1_0 / iio0_0 / iio1_0 p1_1 / iio0_1 / iio1_1 p1_2 / iio0_2 / iio1_2 p2_2 / an2_2 / iio0_2 p2_3 / an2_3 / iio0_3 p2_4 / an2_4 / iio0_4 p2_5 / an2_5 / iio0_5 p2_6 / an2_6 / iio0_6 p2_7 / an2_7 / iio0_7 p6_0 / tb0in / cts0 / rts0 / ss0 p6_1 / tb1in / clk0 p6_2 / tb2in / rxd0 / scl0 / stxd0 p6_3 / txd0 / sda0 / srxd0 p3_0 / ta0out / clk3 / ud0a / ud1a p3_1 / ta3out / rxd3 / scl3 / stxd3 / ud0b / ud1b p3_2 / ta1out / v / txd3 / sda3 / srxd3 p3_3 / ta1in / v / cts3 / rts3 / ss3 p1_3 / iio0_3 / iio1_3 p1_4 / iio0_4 / iio1_4 p1_5 / adtrg / int3 / iio0_5 / iio1_5 p1_6 / int4 / iio0_6 / iio1_6 p1_7 / int5 / iio0_7 / iio1_7 p2_0 / an2_0 / iio0_0 p2_1 / an2_1 / iio0_1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 an0_2 / p0_2 r32c/111 group plqp0080kb-a (80p6q-a) (top view) (note 2) notes: 1. pins p7_0 and p7_1 are open drain outputs. 2. the position of pin number 1 varies by product. refer to the index mark in attached ?package dimensions?. (note 1)
r01ds0062ej0120 rev.1.20 page 19 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.11 pin characteristics for the 80-pin package (1/2) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin analog pin 1 p9_5 clk4 anex0 2 p9_3 tb3in da0 3vdc0 4vdc1 5nsd 6 cnvss 7 xcin p8_7 8 xcout p8_6 9 reset 10 xout 11 vss 12 xin 13 vcc1 14 p8_5 nmi 15 p8_4 int2 16 p8_3 int1 17 p8_2 int0 18 p8_1 ta4in/ ucts5 / rts5 / ss5 iio1_5/ud0b/ud1b 19 p8_0 ta4out/u rxd5/scl5/stxd5 ud0a/ud1a 20 p7_7 ta3in clk5 iio1_4/ud0b/ud1b 21 p7_6 ta3out txd5/sda5/srxd5/ cts8 / rts8 iio1_3/ud0a/ud1a 22 p7_5 ta2in/ w rxd8 iio1_2 23 p7_4 ta2out/w clk8 iio1_1 24 p7_3 ta1in/ vcts2 / rts2 / ss2 /txd8 iio1_0 25 p7_2 ta1out/v clk2 26 p7_1 ta0in/tb5in rxd2/sc l2/stxd2 iio1_7/outc2_2/ isrxd2/iein 27 p7_0 ta0out txd2/sda2/srxd2 iio1_6/outc2_0/ istxd2/ieout 28 p6_7 txd1/sda1/srxd1 29 p6_6 rxd1/scl1/stxd1 30 p6_5 clk1 31 p6_4 cts1 / rts1 / ss1 outc2_1/isclk2 32 p3_7 ta4in/ u 33 p3_6 ta4out/u 34 p3_5 ta2in/ w 35 p3_4 ta2out/w 36 p3_3 ta1in/ vcts3 / rts3 / ss3 37 p3_2 ta1out/v txd3/sda3/srxd3 38 p3_1 ta3out rxd3/scl3/stxd3 ud0b/ud1b 39 p3_0 ta0out clk3 ud0a/ud1a 40 p6_3 txd0/sda0/srxd0
r01ds0062ej0120 rev.1.20 page 20 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.12 pin characteristics for the 80-pin package (2/2) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin analog pin 41 p6_2 tb2in rxd0/scl0/stxd0 42 p6_1 tb1in clk0 43 p6_0 tb0in cts0 / rts0 / ss0 44 p2_7 iio0_7 an2_7 45 p2_6 iio0_6 an2_6 46 p2_5 iio0_5 an2_5 47 p2_4 iio0_4 an2_4 48 p2_3 iio0_3 an2_3 49 p2_2 iio0_2 an2_2 50 p2_1 iio0_1 an2_1 51 p2_0 iio0_0 an2_0 52 p1_7 int5 iio0_7/iio1_7 53 p1_6 int4 iio0_6/iio1_6 54 p1_5 int3 iio0_5/iio1_5 adtrg 55 p1_4 iio0_4/iio1_4 56 p1_3 iio0_3/iio1_3 57 p1_2 iio0_2/iio1_2 58 p1_1 iio0_1/iio1_1 59 p1_0 iio0_0/iio1_0 60 p0_7 an0_7 61 p0_6 an0_6 62 p0_5 an0_5 63 p0_4 an0_4 64 p0_3 an0_3 65 p0_2 an0_2 66 p0_1 an0_1 67 p0_0 an0_0 68 p10_7 ki3 an_7 69 p10_6 ki2 an_6 70 p10_5 ki1 an_5 71 p10_4 ki0 an_4 72 p10_3 an_3 73 p10_2 an_2 74 p10_1 an_1 75 avss 76 p10_0 an_0 77 vref 78 avcc 79 p9_7 rxd4/scl4/stxd4 adtrg 80 p9_6 txd4/sda4/srxd4 anex1
r01ds0062ej0120 rev.1.20 page 21 of 99 sep 26, 2011 r32c/111 group 1. overview figure 1.8 pin assignment for the 64-pin package (top view) 17 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 64 63 62 61 60 59 58 57 56 55 54 53 51 50 49 52 an_1 / p10_1 p7_6 / ta3out / txd5 / sda5 / srxd5 / cts8 / rts8 / iio1_3 / ud0a / ud1a p7_5 / ta2in / w / rxd8 / iio1_2 avcc vref avss an_2 / p10_2 an_3 / p10_3 ki0 / an_4 / p10_4 ki1 / an_5 / p10_5 ki2 / an_6 / p10_6 ki3 / an_7 / p10_7 an0_0 / p0_0 an0_1 / p0_1 p7_4 / ta2out / w / clk8 / iio1_1 p7_3 / ta1in / v / cts2 / rts2 / ss2 / txd8 / iio1_0 p7_2 / ta1out / v / clk2 p7_1 / ta0in / tb5in / rxd2 / scl2 / stxd2 / iio1_7 / outc2_2 / isrxd2 / iein p7_0 / ta0out / txd2 / sda2 / srxd2 / iio1_6 / outc2_0 / istxd2 / ieout (note 1) p6_7 / txd1 / sda1 / srxd1 p6_6 / rxd1 / scl1 / stxd1 p6_5 / clk1 p6_4 / cts1 / rts1 / ss1 / outc2_1 / isclk2 an_0 / p10_0 tb3in / da0 / p9_3 vdc0 nsd cnvss xcin / p8_7 xcout / p8_6 reset xout vss xin vcc1 nmi / p8_5 int2 / p8_4 int1 / p8_3 int0 / p8_2 iio1_5 / ud0b / ud1b / cts5 / rts5 / ss5 / u / ta4in / p8_1 ud0a / ud1a / rxd5 / scl5 / stxd5 / u / ta4out / p8_0 vdc1 p0_3 / an0_3 p1_5 / adtrg / int3 / iio0_5 / iio1_5 p1_6 / int4 / iio0_6 / iio1_6 p1_7 / int5 / iio0_7 / iio1_7 p2_7 / an2_7 / iio0_7 p6_0 / tb0in / cts0 / rts0 / ss0 p6_1 / tb1in / clk0 p6_2 / tb2in / rxd0 / scl0 / stxd0 p6_3 / txd0 / sda0 / srxd0 p3_0 / ta0out / clk3 / ud0a / ud1a p3_1 / ta3out / rxd3 / scl3 / stxd3 / ud0b / ud1b p3_2 / ta1out / v / txd3 / sda3 / srxd3 p3_3 / ta1in / v / cts3 / rts3 / ss3 p2_0 / an2_0 / iio0_0 p2_1 / an2_1 / iio0_1 p2_2 / an2_2 / iio0_2 p2_3 / an2_3 / iio0_3 p2_4 / an2_4 / iio0_4 p2_5 / an2_5 / iio0_5 p2_6 / an2_6 / iio0_6 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 an0_2 / p0_2 r32c/111 group plqp0064kb-a (64p6q-a) (top view) (note 2) notes: 1. pins p7_0 and p7_1 are open drain outputs. 2. the position of pin number 1 varies by product. refer to the index mark in attached ?package dimensions?. p7_7 / ta3in / clk5 / iio1_4 / ud0b / ud1b (note 1)
r01ds0062ej0120 rev.1.20 page 22 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.13 pin characteristics for the 64-pin package (1/2) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin analog pin 1vdc1 2nsd 3 cnvss 4 xcin p8_7 5 xcout p8_6 6 reset 7xout 8 vss 9xin 10 vcc1 11 p8_5 nmi 12 p8_4 int2 13 p8_3 int1 14 p8_2 int0 15 p8_1 ta4in/ ucts5 / rts5 / ss5 iio1_5/ud0b/ud1b 16 p8_0 ta4out/u rxd5/scl5/stxd5 ud0a/ud1a 17 p7_7 ta3in clk5 iio1_4/ud0b/ud1b 18 p7_6 ta3out txd5/sda5/srxd5/ cts8 / rts8 iio1_3/ud0a/ud1a 19 p7_5 ta2in/ w rxd8 iio1_2 20 p7_4 ta2out/w clk8 iio1_1 21 p7_3 ta1in/ vcts2 / rts2 / ss2 /txd8 iio1_0 22 p7_2 ta1out/v clk2 23 p7_1 ta0in/ tb5in rxd2/scl2/stxd2 iio1_7/outc2_2/ isrxd2/iein 24 p7_0 ta0out txd2/sda2/srxd2 iio1_6/outc2_0/ istxd2/ieout 25 p6_7 txd1/sda1/srxd1 26 p6_6 rxd1/scl1/stxd1 27 p6_5 clk1 28 p6_4 cts1 / rts1 / ss1 outc2_1/isclk2 29 p3_3 ta1in/ vcts3 / rts3 / ss3 30 p3_2 ta1out/v txd3/sda3/srxd3 31 p3_1 ta3out rxd3/scl3/stxd3 ud0b/ud1b 32 p3_0 ta0out clk3 ud0a/ud1a 33 p6_3 txd0/sda0/srxd0 34 p6_2 tb2in rxd0/scl0/stxd0 35 p6_1 tb1in clk0 36 p6_0 tb0in cts0 / rts0 / ss0 37 p2_7 iio0_7 an2_7 38 p2_6 iio0_6 an2_6 39 p2_5 iio0_5 an2_5 40 p2_4 iio0_4 an2_4
r01ds0062ej0120 rev.1.20 page 23 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.14 pin characteristics for the 64-pin package (2/2) pin no. control pin port interrupt pin timer pin uart pin intelligent i/o pin analog pin 41 p2_3 iio0_3 an2_3 42 p2_2 iio0_2 an2_2 43 p2_1 iio0_1 an2_1 44 p2_0 iio0_0 an2_0 45 p1_7 int5 iio0_7/iio1_7 46 p1_6 int4 iio0_6/iio1_6 47 p1_5 int3 iio0_5/iio1_5 adtrg 48 p0_3 an0_3 49 p0_2 an0_2 50 p0_1 an0_1 51 p0_0 an0_0 52 p10_7 ki3 an_7 53 p10_6 ki2 an_6 54 p10_5 ki1 an_5 55 p10_4 ki0 an_4 56 p10_3 an_3 57 p10_2 an_2 58 p10_1 an_1 59 avss 60 p10_0 an_0 61 vref 62 avcc 63 p9_3 tb3in da0 64 vdc0
r01ds0062ej0120 rev.1.20 page 24 of 99 sep 26, 2011 r32c/111 group 1. overview 1.5 pin definitions and functions table 1.15 to table 1.21 show the pin definitions and functions. table 1.15 pin definitions and functi ons for the 100-pin package (1/4) function symbol i/o power supply description power supply vcc1, vcc2, vss i? applicable as follows: vcc1 and vcc2 = 3.0 to 5.5 v (vcc1 vcc2), vss = 0 v connecting pins for decoupling capacitor vdc0, vdc1 ?? a decoupling capacitor for internal voltage should be connected between vdc0 and vdc1 analog power supply avcc, avss i vcc1 power supply for the a/d converter. avcc and avss should be connected to vcc1 and vss, respectively reset input reset i vcc1 the mcu is reset when this pin is driven low cnvss cnvss i vcc1 this pin should be connected to vss via a resistor debug port nsd i/o vcc1 this pin is to communicate with a debugger. it should be connected to vcc1 via a resistor of 1 to 4.7 k main clock input xin i vcc1 input/output for the main cl ock oscillator. a crystal, or a ceramic resonator should be connected between pins xin and xout. an external clock should be input at the xin while leaving the xout open main clock output xout o vcc1 sub clock input xcin i vcc1 input/output for the sub cl ock oscillator. a crystal oscillator should be connected between pins xcin and xcout. an external cl ock should be input at the xcin while leaving the xcout open sub clock output xcout o vcc1 bclk output bclk o vcc2 bclk output clock output clkout o vcc2 output of the clock with the same frequency as low speed clocks, f8, or f32 external interrupt input int0 to int5 i vcc1 vcc2 input for external interrupts nmi input p8_5/ nmi i vcc1 input for nmi key input interrupt ki0 to ki3 i vcc1 input for the key input interrupt bus control pins d0 to d7 i/o vcc2 input/output of data (d0 to d7) while accessing an external memory space with a separate bus d8 to d15 i/o vcc2 input/output of data (d8 to d15) while accessing an external memory spac e with 16-bit separate bus a0 to a23 o vcc2 output of address bits a0 to a23
r01ds0062ej0120 rev.1.20 page 25 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.16 pin definitions and functi ons for the 100-pin package (2/4) function symbol i/o power supply description bus control pins a0/d0 to a7/d7 i/o vcc2 output of address bits (a 0 to a7) and input/output of data (d0 to d7) by ti me-division while accessing an external memory space with multiplexed bus a8/d8 to a15/d15 i/o vcc2 output of address bits (a8 to a15) and input/ output of data (d8 to d15) by time-division while accessing an external me mory space with 16-bit multiplexed bus bc0 /d0 i/o vcc2 output of byte control ( bc0 ) and input/output of data (d0) by time-divis ion while accessing an external memory space with multiplexed bus cs0 to cs3 o vcc2 chip select output wr0 / wr1 / wr / bc0 / bc1 / rd o vcc2 output of write, byte control, and read signals. either wrx or wr and bcx can be selected by a program. data is read when rd is low. ? when wr0 , wr1 , and rd are selected, data is written to the following address: an even address, when wr0 is low an odd address, when wr1 is low on 16-bit external data bus ? when wr , bc0 , bc1 , and rd are selected, data is written, when wr is low and the following address is accessed: an even address, when bc0 is low an odd address, when bc1 is low on 16-bit external data bus ale o vcc2 latch enable signal in multiplexed bus format hold i vcc2 the mcu is in a hold stat e while this pin is held low hlda o vcc2 this pin is driven low wh ile the mcu is held in a hold state rdy i vcc2 bus cycle is extended by the cpu if this pin is low on the falling edge of bclk
r01ds0062ej0120 rev.1.20 page 26 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.17 pin definitions and functi ons for the 100-pin package (3/4) function symbol i/o power supply description i/o port p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, i/o vcc2 i/o ports in cmos. each port can be programmed to input or output under the control of the direction register. pull-up resistors are sele cted for following 4-pin units, but are enabled only for the input pins: pi_0 to pi_3 and pi_4 to pi_7 (i = 0 to 10). p7_0 and p7_1 outputs are n-channel open drain p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 i/o vcc1 input port p9_1 i vcc1 input port in cmos. pull-up resistors are selectable for p9_1 and p9_3 timer a ta0out to ta4out i/o vcc1 vcc2 timers a0 to a4 input/output. ta0out output assigned for port p7_0 is n- channel open drain ta0in to ta4in i vcc1 vcc2 timers a0 to a4 input timer b tb0in to tb5in i vcc1 timers b0 to b5 input three-phase motor control timer output u, u ,v, v ,w, w o vcc1 vcc2 three-phase motor control timer output serial interface cts0 to cts8 i vcc1 vcc2 handshake input rts0 to rts8 o vcc1 vcc2 handshake output clk0 to clk8 i/o vcc1 vcc2 transmit/receive clock input/output rxd0 to rxd8 i vcc1 vcc2 serial data input txd0 to txd8 o vcc1 vcc2 serial data output. txd2 output is n-channel open drain i 2 c bus (simplified) sda0 to sda6 i/o vcc1 vcc2 serial data input/output. sda2 output is n-channel open drain scl0 to scl6 i/o vcc1 vcc2 transmit/receive clock input/output. scl2 output is n-channel open drain
r01ds0062ej0120 rev.1.20 page 27 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.18 pin definitions and functi ons for the 100-pin package (4/4) function symbol i/o power supply description serial interface special functions stxd0 to stxd6 o vcc1 vcc2 serial data output in slave mode. stxd2 is n-channel open drain srxd0 to srxd6 i vcc1 vcc2 serial data input in slave mode ss0 to ss6 i vcc1 vcc2 input to control serial interface special functions a/d converter an_0 to an_7 i vcc1 analog input for the a/d converter an0_0 to an0_7, an2_0 to an2_7 i vcc2 adtrg i vcc1 external trigger input for the a/d converter anex0 i/o vcc1 expanded analog input for the a/d converter and output in external op -amp connection mode anex1 i vcc1 expanded analog input for the a/d converter d/a converter da0, da1 o vcc1 ou tput for the d/a converter reference voltage input vref i ? reference voltage input for the a/d converter and d/a converter intelligent i/o iio0_0 to iio0_7 i/o vcc1 vcc2 input/output for the intellig ent i/o group 0. either input capture or output compare is selectable iio1_0 to iio1_7 i/o vcc1 vcc2 input/output for the intellig ent i/o group 1. either input capture or output compare is selectable. iio1_6 and iio1_7 outputs assigned for ports p7_0 and p7_1 are n-channel open drain ud0a, ud0b, ud1a, ud1b i vcc1 vcc2 input for the two-phase encoder outc2_0 to outc2_2 o vcc1 vcc2 output for oc ( output compare) of the intelligent i/ o group 2. outc2_0 and outc2_2 assigned for ports p7_0 and p7_1 are n-channel open drain isclk2 i/o vcc1 vcc2 clock input/output for the serial interface isrxd2 i receive data input for the serial interface istxd2 o transmit data output fo r the serial interface. istxd2 assigned for port p7_0 is n-channel open drain iein i vcc1 vcc2 receive data input for the serial interface ieout o transmit data output fo r the serial interface. ieout assigned for port p7_0 is n-channel open drain
r01ds0062ej0120 rev.1.20 page 28 of 99 sep 26, 2011 r32c/111 group 1. overview note: 1. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 80-pin package only. table 1.19 pin definitions and functions for the 80-/64-pin package (1/3) function symbol i/o description power supply vcc1, vss i applicable as follo ws: vcc1 = 3.0 to 5.5 v, vss = 0 v connecting pins for decoupling capacitor vdc0, vdc1 ? a decoupling capacitor for internal voltage should be connected between vdc0 and vdc1 analog power supply avcc, avss i power supply for th e a/d converter. avcc and avss should be connected to vcc and vss, respectively reset input reset i the mcu is reset when this pin is driven low cnvss cnvss i this pin should be co nnected to vss via a resistor debug port nsd i/o this pin is to communicate with a debugger. it should be connected to vcc1 via a resistor of 1 to 4.7 k main clock input xin i input/output for the main clock oscillator. a crystal, or a ceramic resonator should be connected between pins xin and xout. an external clock should be input at the xin while leaving the xout open main clock output xout o sub clock input xcin i input/output for the sub clock o scillator. a crystal oscillator should be connected between pins xcin and xcout. an external clock should be input at the xcin while leaving the xcout open sub clock output xcout o external interrupt input int0 to int5 i input for external interrupts nmi input p8_5/ nmi i input for nmi key input interrupt ki0 to ki3 i input for the key input interrupt i/o port (1) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3, p9_5 to p9_7, p10_0 to p10_7 i/o i/o ports in cmos. each port can be programmed to input or output under the control of the direction register. pull-up resistors are selected for following 4-pin units, but are enabled only for the input pins: pi_0 to pi_3 and pi_4 to pi_7 (i = 0 to 3, 6 to 10). p7_0 and p7_1 outputs are n-channel open drain timer a ta0out to ta4out i/o timers a0 to a4 input/output. ta0out output assigned for port p7_0 is n-channel open drain ta0in to ta4in i timers a0 to a4 input timer b tb0in to tb3in, tb5in i timers b0 to b3 , and b5 input three-phase motor control timer output u, u , v, v , w, w o three-phase motor control timer output
r01ds0062ej0120 rev.1.20 page 29 of 99 sep 26, 2011 r32c/111 group 1. overview notes: 1. pins clk4, rxd4, txd4, sda4, scl4, srxd4, and stxd4 are available in the 80-pin package only. 2. pins an0_4 to an0_7, anex0 and anex1 are available in the 80-pin package only. table 1.20 pin definitions and functions for the 80-/64-pin package (2/3) function symbol i/o description serial interface (1) cts0 to cts3 , cts5 , cts8 i handshake input rts0 to rts3 , rts5 , rts8 o handshake output clk0 to clk5, clk8 i/o transmit/receive clock input/output rxd0 to rxd5, rxd8 i serial data input txd0 to txd5, txd8 o serial data output. txd2 output is n-channel open drain i 2 c bus (simplified) (1) sda0 to sda5 i/o serial data input/output. sda2 output is n-channel open drain scl0 to scl5 i/o transmit/receive clock input/output. scl2 output is n-channel open drain serial interface special functions (1) stxd0 to stxd5 o serial data output in slave mode. stxd2 is n-channel open drain srxd0 to srxd5 i serial data input in slave mode ss0 to ss3 , ss5 i input to control serial interface special functions a/d converter (2) an_0 to an_7, an0_0 to an0_7, an2_0 to an2_7 i analog input for the a/d converter adtrg i external trigger input for the a/d converter anex0 i/o expanded analog input for the a/d converter and output in external op-amp connection mode anex1 i expanded analog input for the a/d converter d/a converter da0 o output for the d/a converter reference voltage input vref i reference voltage input for the a/d converter and d/a converter
r01ds0062ej0120 rev.1.20 page 30 of 99 sep 26, 2011 r32c/111 group 1. overview table 1.21 pin definitions and functions for the 80-/64-pin package (3/3) function symbol i/o description intelligent i/o iio0_0 to iio0_7 i/o input/output for the intelligent i/o group 0. either input capture or output compare is selectable iio1_0 to iio1_7 i/o input/output for the intelligent i/o group 1. either input capture or output compare is selectable. iio1_6 and iio1_7 outputs assigned for ports p7_0 and p7_1 are n-channel open drain ud0a, ud0b, ud1a, ud1b i input for the two-phase encoder outc2_0 to outc2_2 o output for oc (output compare) of th e intelligent i/o group 2. outc2_0 and outc2_2 assigned for ports p7_0 and p7_1 are n-channel open drain isclk2 i/o clock input/output for the serial interface isrxd2 i receive data input for the serial interface istxd2 o transmit data output for the serial interface. istxd2 assigned for port p7_0 is n-channel open drain iein i receive data input for the serial interface ieout o transmit data output for th e serial interface. ieout assigned for port p7_0 is n-channel open drain
r01ds0062ej0120 rev.1.20 page 31 of 99 sep 26, 2011 r32c/111 group 2. central processing unit (cpu) 2. central processi ng unit (cpu) the cpu contains the registers shown below. there ar e two register banks each consisting of registers r2r0, r3r1, r6r4, r7r5, a0 to a3, sb, and fb. figure 2.1 cpu registers dda0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dda0 dcr0 dct0 dmd0 ddr0 dsa0 dsr0 dcr0 dct0 dmd0 b0 b31 vct svp svf pc intb usp isp fb sb a3 a2 a1 r5 r7 r6 r4 r1l r1h r3l r3h r2h r2l r0h r0l a0 flg b0 b31 general purpose registers fast interrupt registers dmac-associated registers (2) notes: 1. there are two banks of these registers. 2. there are four identical sets of dmac-associated registers. dma destination address reload register flag register data registers (1) address registers (1) static base register (1) frame base register (1) user stack pointer interrupt stack pointer interrupt vector table base register program counter save flag register save pc register vector register r2r0 r3r1 r6r4 r7r5 dma source address register dma source address reload register dma terminal count reload register dma terminal count register dma mode register c d z s b o i u ipl rnd b0 b31 b8 b7 b16 b15 b0 b31 b23 b15 b7 dma destination address register blank spaces are reserved. fu fo dp b24 b23 b23
r01ds0062ej0120 rev.1.20 page 32 of 99 sep 26, 2011 r32c/111 group 2. central processing unit (cpu) 2.1 general purpose registers 2.1.1 data registers (r2r0, r3r1, r6r4, and r7r5) these 32-bit registers are primarily used for transfers and arithmetic/logic operations. each of the registers can be divided into upper and lower 16-bit registers, e.g. r2r0 can be divided into r2 and r0, r3r1 can be di vided into r3 and r1, etc. moreover, data registers r2r0 and r3r1 can be divided into four 8-bit data registers: upper (r2h and r3h), mid-upper (r2l and r3l), mid-lower (r0h and r1h), and lower (r0l and r1l). 2.1.2 address registers (a0, a1, a2, and a3) these 32-bit registers have functions similar to data registers. they are also used for address register indirect addressing and address register relative addressing. 2.1.3 static base register (sb) this 32-bit register is used for sb relative addressing. 2.1.4 frame base register (fb) this 32-bit register is used for fb relative addressing. 2.1.5 program counter (pc) this 32-bit counter indicates the address of the instruction to be executed next. 2.1.6 interrupt vector ta ble base register (intb) this 32-bit register indicates the start address of a relocatable vector table. 2.1.7 user stack pointer (usp) a nd interrupt stack pointer (isp) two types of 32-bit stack pointers (sps) are provided: user stack pointer (usp) and interrupt stack pointer (isp). use the stack pointer select flag (u flag) to select either the user stack point er (usp) or the interrupt stack pointer (isp). the u flag is bit 7 in the flag register (flg). refer to 2.1.8 ?flag register (flg)? for details. to minimize the overhead of interrupt sequence due to less memory access, se t the user stack pointer (usp) or the interrupt stack pointer (isp) to a multiple of 4. 2.1.8 flag register (flg) this 32-bit register indicates the cpu status. 2.1.8.1 carry flag (c flag) this flag retains a carry, borrow, or shifted-out bit generated by the arithmetic logic unit (alu). 2.1.8.2 debug flag (d flag) this flag is only for debugging. only set this bit to 0. 2.1.8.3 zero flag (z flag) this flag becomes 1 when the result of an operation is 0; otherwise it is 0. 2.1.8.4 sign flag (s flag) this flag becomes 1 when the result of an operation is a negative value; otherwise it is 0.
r01ds0062ej0120 rev.1.20 page 33 of 99 sep 26, 2011 r32c/111 group 2. central processing unit (cpu) 2.1.8.5 register bank se lect flag (b flag) this flag selects a register bank. it indicates 0 w hen register bank 0 is selected, and 1 when register bank 1 is selected. 2.1.8.6 overflow flag (o flag) this flag becomes 1 when the result of an operation overflows; otherwise it is 0. 2.1.8.7 interrupt enab le flag (i flag) this flag enables maskable interrupts. to disable mask able interrupts, set this flag to 0. to enable them, set this flag to 1. when an in terrupt is accepted, the flag becomes 0. 2.1.8.8 stack pointer se lect flag (u flag) to select the interrupt stack pointer (isp), set this flag to 0. to select the user sta ck pointer (usp), set this flag to 1. it becomes 0 when a hardware interrupt is accepted or when an int instruction designated by a software interrupt number from 0 to 127 is executed. 2.1.8.9 floating-point u nderflow flag (fu flag) this flag becomes 1 when an underflow occurs in a floating-point operation; otherwise it is 0. it also becomes 1 when the operand contains invalid numbers (subnormal numbers). 2.1.8.10 floating-point o verflow flag (fo flag) this flag becomes 1 when an overflow occurs in a floating-point operation; otherwise it is 0. it also becomes 1 when the operand contains invalid numbers (subnormal numbers). 2.1.8.11 processor interrup t priority level (ipl) the processor interrupt priority level (ipl), consi sting of 3 bits, selects a processor interrupt priority level from level 0 to 7. an interrupt is enabled when the interrupt request level is higher than the selected ipl. when the processor interrupt priority level (ipl) is set to 111b (level 7), all interrupts are disabled. 2.1.8.12 fixed-point radix po int designation bit (dp bit) this bit designates the radix point. it also specifies which portion of the fixed-point multiplication result to extract. it is used fo r the mulx instruction. 2.1.8.13 floating-point rounding mode (rnd) the 2-bit floating-point rounding mode selects a rounding mode for floating-point calculation results. 2.1.8.14 reserved only set this bit to 0. th e read value is undefined.
r01ds0062ej0120 rev.1.20 page 34 of 99 sep 26, 2011 r32c/111 group 2. central processing unit (cpu) 2.2 fast interrupt registers the following three registers are provided to minimize the overhead of the interrupt sequence. 2.2.1 save flag register (svf) this 32-bit register is used to save the flag register when a fast interrupt is generated. 2.2.2 save pc register (svp) this 32-bit register is used to save the program counter when a fast interrupt is generated. 2.2.3 vector register (vct) this 32-bit register is used to indicate a ju mp address when a fast interrupt is generated. 2.3 dmac-associated registers there are seven types of dmac-associated registers. 2.3.1 dma mode registers (d md0, dmd1, dmd2, and dmd3) these 32-bit registers are used to set dma transfer mode, bit rate, etc. 2.3.2 dma terminal count register s (dct0, dct1, dct2, and dct3) these 24-bit registers are used to set the number of dma transfers. 2.3.3 dma terminal count reload regi sters (dcr0, dcr1 , dcr2, and dcr3) these 24-bit registers are used to set the reloaded values for dma terminal count registers. 2.3.4 dma source address register s (dsa0, dsa1, dsa2, and dsa3) these 32-bit registers are used to set dma source addresses. 2.3.5 dma source address reload regi sters (dsr0, dsr1, dsr2, and dsr3) these 32-bit registers are used to set the reloaded values for dma source address registers. 2.3.6 dma destination a ddress registers (dda0, dda1, dda2, and dda3) these 32-bit registers are used to set dma destination addresses. 2.3.7 dma destination address reload registers (ddr0, ddr1, ddr2, and ddr3) these 32-bit registers are used to set reloaded values for dma destination address registers.
r01ds0062ej0120 rev.1.20 page 35 of 99 sep 26, 2011 r32c/111 group 3. memory 3. memory figure 3.1 shows the memory map of the r32c/111 group. the r32c/111 group provides a 4-gbyte address space from 00000000h to ffffffffh. the internal rom is mapped from address ffffffffh in the inferior direction. for example, the 512-kbyte internal rom is mapped from fff80000h to ffffffffh. the fixed interrupt vector table contains the start address of interrupt handlers and is mapped from ffffffdch to ffffffffh. the internal ram is mapped from address 00000400h in the superior direction. for example, the 63-kbyte internal ram is mapped from 00000400h to 0000ffffh. besides being used for data storage, the internal ram functions as a stack(s) for subrout ine calls and/or interrupt handlers. special function registers (sfrs), which are contro l registers for peripheral functions, are mapped from 00000000h to 000003ffh, and from 00040000h to 0004ffffh. unoccupied sfr locations are reserved, and no access is allowed. in memory expansion mode or microprocessor mode, so me spaces are reserved for internal use and should not be accessed. figure 3.1 memory map internal ram sfr1 sfr2 00000000h ffffffffh reset nmi reserved reserved reserved brk instruction overflow undefined instruction watchdog timer (5) ffffffffh ffffffdch yyyyyyyyh 00000400h xxxxxxxxh reserved 00040000h internal rom (data space) (1) 00060000h 00062000h 00050000h reserved internal rom capacity yyyyyyyyh 512 kbytes fff80000h external space (2) reserved 00080000h reserved (3) ffe00000h internal rom (4) 384 kbytes fffa0000h notes: 1. the flash memory version provides two additional 4-kbyte spaces (blocks a and b) for storing data. 2. this space can be used in memory expansion mode or microprocessor mode. addresses from 02000000h to fdffffffh are inaccessible. 3. this space is reserved in memory expansion mode. it becomes an external space in microprocessor mode. 4. this space can be used in single-chip mode or memory expansion mode. it becomes an external space in microprocessor mode. 5. the watchdog timer interrupt shares a vector with the oscillator stop detection interrupt and low voltage detection interrupt. 256 kbytes fffc0000h internal ram capacity xxxxxxxxh 63 kbytes 00010000h 40 kbytes 0000a400h 32 kbytes 00008400h 128 kbytes fffe0000h
r01ds0062ej0120 rev.1.20 page 36 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) 4. special function registers (sfrs) sfrs are memory-mapped peripheral registers that c ontrol the operation of peripherals. table 4.1 sfr list (1) to table 4.24 sfr list (24) list the sfr details. table 4.1 sfr list (1) address register symbol reset value 000000h 000001h 000002h 000003h 000004h clock control register ccr 0001 1000b 000005h 000006h flash memory control register fmcr 0000 0001b 000007h protect release register prr 00h 000008h 000009h 00000ah 00000bh 00000ch 00000dh 00000eh 00000fh 000010h external bus control register 3/flash memory rewrite bus control register 3 ebc3/febc3 0000h 000011h 000012h chip selects 2 and 3 boundary setting register cb23 00h 000013h 000014h external bus control register 2 ebc2 0000h 000015h 000016h chip selects 1 and 2 boundary setting register cb12 00h 000017h 000018h external bus control register 1 ebc1 0000h 000019h 00001ah chip selects 0 and 1 boundary setting register cb01 00h 00001bh 00001ch external bus control register 0/flash memory rewrite bus control register 0 ebc0/febc0 0000h 00001dh 00001eh peripheral bus control register pbc 0504h 00001fh 000020h to 00005fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 37 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.2 sfr list (2) address register symbol reset value 000060h 000061h timer b5 interrupt control register tb5ic xxxx x000b 000062h uart5 transmit/nack interrupt control register s5tic xxxx x000b 000063h uart2 receive/ack interrupt control register s2ric xxxx x000b 000064h uart6 transmit/nack interrupt control register s6tic xxxx x000b 000065h uart3 receive/ack interrupt control register s3ric xxxx x000b 000066h uart5/6 bus collision, start condition/stop condition detection interrupt control register bcn5ic/bcn6ic xxxx x000b 000067h uart4 receive/ack interrupt control register s4ric xxxx x000b 000068h dma0 transfer complete interr upt control register dm0ic xxxx x000b 000069h uart0/3 bus collision, start condition/stop condition detection interrupt control register bcn0ic/bcn3ic xxxx x000b 00006ah dma2 transfer complete interr upt control register dm2ic xxxx x000b 00006bh a/d converter 0 convert comple tion interrupt control register ad0ic xxxx x000b 00006ch timer a0 interrupt co ntrol register ta0ic xxxx x000b 00006dh intelligent i/o interrupt c ontrol register 0 iio0ic xxxx x000b 00006eh timer a2 interrupt control register ta2ic xxxx x000b 00006fh intelligent i/o interrupt c ontrol register 2 iio2ic xxxx x000b 000070h timer a4 interrupt control register ta4ic xxxx x000b 000071h intelligent i/o interrupt c ontrol register 4 iio4ic xxxx x000b 000072h uart0 receive/ack interrupt control register s0ric xxxx x000b 000073h intelligent i/o interrupt c ontrol register 6 iio6ic xxxx x000b 000074h uart1 receive/ack interrupt control register s1ric xxxx x000b 000075h intelligent i/o interrupt c ontrol register 8 iio8ic xxxx x000b 000076h timer b1 interrupt control register tb1ic xxxx x000b 000077h intelligent i/o interrupt cont rol register 10 iio10ic xxxx x000b 000078h timer b3 interrupt control register tb3ic xxxx x000b 000079h 00007ah int5 interrupt control register int5ic xx00 x000b 00007bh 00007ch int3 interrupt control register int3ic xx00 x000b 00007dh 00007eh int1 interrupt control register int1ic xx00 x000b 00007fh 000080h 000081h uart2 transmit/nack interrupt control register s2tic xxxx x000b 000082h uart5 receive/ack interrupt control register s5ric xxxx x000b 000083h uart3 transmit/nack interrupt control register s3tic xxxx x000b 000084h uart6 receive/ack interrupt control register s6ric xxxx x000b 000085h uart4 transmit/nack interrupt control register s4tic xxxx x000b 000086h 000087h uart2 bus collision, start condition/stop condition detection interrupt control register bcn2ic xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 38 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.3 sfr list (3) address register symbol reset value 000088h dma1 transfer complete interr upt control register dm1ic xxxx x000b 000089h uart1/4 bus collision, start condition/stop condition detection interrupt control register bcn1ic/bcn4ic xxxx x000b 00008ah dma3 transfer complete interr upt control register dm3ic xxxx x000b 00008bh key input interrupt control register kupic xxxx x000b 00008ch timer a1 interrupt co ntrol register ta1ic xxxx x000b 00008dh intelligent i/o interrupt c ontrol register 1 iio1ic xxxx x000b 00008eh timer a3 interrupt control register ta3ic xxxx x000b 00008fh intelligent i/o interrupt c ontrol register 3 iio3ic xxxx x000b 000090h uart0 transmit/nack interrupt control register s0tic xxxx x000b 000091h intelligent i/o interrupt c ontrol register 5 iio5ic xxxx x000b 000092h uart1 transmit/nack interrupt control register s1tic xxxx x000b 000093h intelligent i/o interrupt c ontrol register 7 iio7ic xxxx x000b 000094h timer b0 interrupt control register tb0ic xxxx x000b 000095h intelligent i/o interrupt c ontrol register 9 iio9ic xxxx x000b 000096h timer b2 interrupt control register tb2ic xxxx x000b 000097h intelligent i/o interrupt cont rol register 11 iio11ic xxxx x000b 000098h timer b4 interrupt control register tb4ic xxxx x000b 000099h 00009ah int4 interrupt control register int4ic xx00 x000b 00009bh 00009ch int2 interrupt control register int2ic xx00 x000b 00009dh 00009eh int0 interrupt control register int0ic xx00 x000b 00009fh 0000a0h intelligent i/o interrupt requ est register 0 iio0ir 0000 0xx1b 0000a1h intelligent i/o interrupt requ est register 1 iio1ir 0000 0xx1b 0000a2h intelligent i/o interrupt requ est register 2 iio2ir 0000 0x01b 0000a3h intelligent i/o interrupt requ est register 3 iio3ir 0000 xxx1b 0000a4h intelligent i/o interrupt requ est register 4 iio4ir 000x 0xx1b 0000a5h intelligent i/o interrupt requ est register 5 iio5ir 000x 0xx1b 0000a6h intelligent i/o interrupt requ est register 6 iio6ir 000x 0xx1b 0000a7h intelligent i/o interrupt requ est register 7 iio7ir x00x 0xx1b 0000a8h intelligent i/o interrupt requ est register 8 iio8ir xx0x 0xx1b 0000a9h intelligent i/o interrupt requ est register 9 iio9ir 0000 0xx1b 0000aah intelligent i/o interrupt requ est register 10 iio10ir 0000 0xx1b 0000abh intelligent i/o interrupt request register 11 iio11ir 0000 0xx1b 0000ach 0000adh 0000aeh 0000afh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 39 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.4 sfr list (4) address register symbol reset value 0000b0h intelligent i/o interrupt enable register 0 iio0ie 00h 0000b1h intelligent i/o interrupt enable register 1 iio1ie 00h 0000b2h intelligent i/o interrupt enable register 2 iio2ie 00h 0000b3h intelligent i/o interrupt enable register 3 iio3ie 00h 0000b4h intelligent i/o interrupt enable register 4 iio4ie 00h 0000b5h intelligent i/o interrupt enable register 5 iio5ie 00h 0000b6h intelligent i/o interrupt enable register 6 iio6ie 00h 0000b7h intelligent i/o interrupt enable register 7 iio7ie 00h 0000b8h intelligent i/o interrupt enable register 8 iio8ie 00h 0000b9h intelligent i/o interrupt enable register 9 iio9ie 00h 0000bah intelligent i/o interrupt enable register 10 iio10ie 00h 0000bbh intelligent i/o interrupt enable register 11 iio11ie 00h 0000bch 0000bdh 0000beh 0000bfh 0000c0h 0000c1h 0000c2h 0000c3h 0000c4h 0000c5h 0000c6h 0000c7h 0000c8h 0000c9h 0000cah 0000cbh 0000cch 0000cdh 0000ceh 0000cfh 0000d0h 0000d1h 0000d2h 0000d3h 0000d4h 0000d5h 0000d6h 0000d7h 0000d8h 0000d9h 0000dah 0000dbh 0000dch 0000ddh uart7 transmit interrupt control register s7tic xxxx x000b 0000deh 0000dfh uart8 transmit interrupt control register s8tic xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 40 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.5 sfr list (5) address register symbol reset value 0000e0h 0000e1h 0000e2h 0000e3h 0000e4h 0000e5h 0000e6h 0000e7h 0000e8h 0000e9h 0000eah 0000ebh 0000ech 0000edh 0000eeh 0000efh 0000f0h 0000f1h 0000f2h 0000f3h 0000f4h 0000f5h 0000f6h 0000f7h 0000f8h 0000f9h 0000fah 0000fbh 0000fch 0000fdh uart7 receive interrupt control r egister s7ric xxxx x000b 0000feh 0000ffh uart8 receive interrupt control register s8ric xxxx x000b 000100h group 1 time measurement/waveform generation register 0 g1tm0/g1po0 xxxxh 000101h 000102h group 1 time measurement/waveform generation register 1 g1tm1/g1po1 xxxxh 000103h 000104h group 1 time measurement/waveform generation register 2 g1tm2/g1po2 xxxxh 000105h 000106h group 1 time measurement/waveform generation register 3 g1tm3/g1po3 xxxxh 000107h x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 41 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.6 sfr list (6) address register symbol reset value 000108h group 1 time measurement/waveform generation register 4 g1tm4/g1po4 xxxxh 000109h 00010ah group 1 time measurement/waveform generation register 5 g1tm5/g1po5 xxxxh 00010bh 00010ch group 1 time measur ement/waveform generation register 6 g1tm6/g1po6 xxxxh 00010dh 00010eh group 1 time measurement/waveform generation register 7 g1tm7/g1po7 xxxxh 00010fh 000110h group 1 waveform generation control register 0 g1pocr0 0000 x000b 000111h group 1 waveform generation control register 1 g1pocr1 0x00 x000b 000112h group 1 waveform generation control register 2 g1pocr2 0x00 x000b 000113h group 1 waveform generation control register 3 g1pocr3 0x00 x000b 000114h group 1 waveform generation control register 4 g1pocr4 0x00 x000b 000115h group 1 waveform generation control register 5 g1pocr5 0x00 x000b 000116h group 1 waveform generation control register 6 g1pocr6 0x00 x000b 000117h group 1 waveform generation control register 7 g1pocr7 0x00 x000b 000118h group 1 time measurement control register 0 g1tmcr0 00h 000119h group 1 time measurement control register 1 g1tmcr1 00h 00011ah group 1 time measurement control register 2 g1tmcr2 00h 00011bh group 1 time measurement control register 3 g1tmcr3 00h 00011ch group 1 time measurement control register 4 g1tmcr4 00h 00011dh group 1 time measurement control register 5 g1tmcr5 00h 00011eh group 1 time measurement control register 6 g1tmcr6 00h 00011fh group 1 time measurement control register 7 g1tmcr7 00h 000120h group 1 base timer register g1bt xxxxh 000121h 000122h group 1 base timer control register 0 g1bcr0 0000 0000b 000123h group 1 base timer control register 1 g1bcr1 0000 0000b 000124h group 1 time measurement prescaler register 6 g1tpr6 00h 000125h group 1 time measurement prescaler register 7 g1tpr7 00h 000126h group 1 function enable register g1fe 00h 000127h group 1 function select register g1fs 00h 000128h 000129h 00012ah 00012bh 00012ch 00012dh 00012eh 00012fh 000130h to 00013fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 42 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.7 sfr list (7) address register symbol reset value 000140h group 2 waveform generation register 0 g2po0 xxxxh 000141h 000142h group 2 waveform generation register 1 g2po1 xxxxh 000143h 000144h group 2 waveform generation register 2 g2po2 xxxxh 000145h 000146h group 2 waveform generation register 3 g2po3 xxxxh 000147h 000148h group 2 waveform generation register 4 g2po4 xxxxh 000149h 00014ah group 2 waveform generation register 5 g2po5 xxxxh 00014bh 00014ch group 2 waveform gene ration register 6 g2po6 xxxxh 00014dh 00014eh group 2 waveform generation register 7 g2po7 xxxxh 00014fh 000150h group 2 waveform generation control register 0 g2pocr0 0000 0000b 000151h group 2 waveform generation control register 1 g2pocr1 0000 0000b 000152h group 2 waveform generation control register 2 g2pocr2 0000 0000b 000153h group 2 waveform generation control register 3 g2pocr3 0000 0000b 000154h group 2 waveform generation control register 4 g2pocr4 0000 0000b 000155h group 2 waveform generation control register 5 g2pocr5 0000 0000b 000156h group 2 waveform generation control register 6 g2pocr6 0000 0000b 000157h group 2 waveform generation control register 7 g2pocr7 0000 0000b 000158h 000159h 00015ah 00015bh 00015ch 00015dh 00015eh 00015fh 000160h group 2 base timer register g2bt xxxxh 000161h 000162h group 2 base timer control register 0 g2bcr0 0000 0000b 000163h group 2 base timer control register 1 g2bcr1 0000 0000b 000164h base timer start register btsr xxxx 0000b 000165h 000166h group 2 function enable register g2fe 00h 000167h group 2 rtp output buffer register g2rtp 00h 000168h 000169h 00016ah group 2 serial interface mode register g2mr 00xx x000b 00016bh group 2 serial interface control register g2cr 0000 x110b 00016ch group 2 si/o transmit buffer register g2tb xxxxh 00016dh 00016eh group 2 si/o receive buffer register g2rb xxxxh 00016fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 43 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.8 sfr list (8) address register symbol reset value 000170h group 2 iebus address register iear xxxxh 000171h 000172h group 2 iebus control register iecr 00xx x000b 000173h group 2 iebus transmit interrupt source detect register ietif xxx0 0000b 000174h group 2 iebus receive interrupt source detect register ierif xxx0 0000b 000175h 000176h 000177h 000178h 000179h 00017ah 00017bh 00017ch 00017dh 00017eh 00017fh 000180h group 0 time measurement/waveform generation register 0 g0tm0/g0po0 xxxxh 000181h 000182h group 0 time measurement/waveform generation register 1 g0tm1/g0po1 xxxxh 000183h 000184h group 0 time measurement/waveform generation register 2 g0tm2/g0po2 xxxxh 000185h 000186h group 0 time measurement/waveform generation register 3 g0tm3/g0po3 xxxxh 000187h 000188h group 0 time measurement/waveform generation register 4 g0tm4/g0po4 xxxxh 000189h 00018ah group 0 time measurement/waveform generation register 5 g0tm5/g0po5 xxxxh 00018bh 00018ch group 0 time measur ement/waveform generation register 6 g0tm6/g0po6 xxxxh 00018dh 00018eh group 0 time measurement/waveform generation register 7 g0tm7/g0po7 xxxxh 00018fh 000190h group 0 waveform generation control register 0 g0pocr0 0000 x000b 000191h group 0 waveform generation control register 1 g0pocr1 0x00 x000b 000192h group 0 waveform generation control register 2 g0pocr2 0x00 x000b 000193h group 0 waveform generation control register 3 g0pocr3 0x00 x000b 000194h group 0 waveform generation control register 4 g0pocr4 0x00 x000b 000195h group 0 waveform generation control register 5 g0pocr5 0x00 x000b 000196h group 0 waveform generation control register 6 g0pocr6 0x00 x000b 000197h group 0 waveform generation control register 7 g0pocr7 0x00 x000b 000198h group 0 time measurement control register 0 g0tmcr0 00h 000199h group 0 time measurement control register 1 g0tmcr1 00h 00019ah group 0 time measurement control register 2 g0tmcr2 00h 00019bh group 0 time measurement control register 3 g0tmcr3 00h 00019ch group 0 time measurement control register 4 g0tmcr4 00h 00019dh group 0 time measurement control register 5 g0tmcr5 00h 00019eh group 0 time measurement control register 6 g0tmcr6 00h 00019fh group 0 time measurement control register 7 g0tmcr7 00h x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 44 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.9 sfr list (9) address register symbol reset value 0001a0h group 0 base timer register g0bt xxxxh 0001a1h 0001a2h group 0 base timer control register 0 g0bcr0 0000 0000b 0001a3h group 0 base timer control register 1 g0bcr1 0000 0000b 0001a4h group 0 time measurement prescaler register 6 g0tpr6 00h 0001a5h group 0 time measurement prescaler register 7 g0tpr7 00h 0001a6h group 0 function enable register g0fe 00h 0001a7h group 0 function select register g0fs 00h 0001a8h 0001a9h 0001aah 0001abh 0001ach 0001adh 0001aeh 0001afh 0001b0h 0001b1h 0001b2h 0001b3h 0001b4h 0001b5h 0001b6h 0001b7h 0001b8h 0001b9h 0001bah 0001bbh 0001bch 0001bdh 0001beh 0001bfh 0001c0h 0001c1h 0001c2h 0001c3h 0001c4h uart5 special mode register 4 u5smr4 00h 0001c5h uart5 special mode register 3 u5smr3 00h 0001c6h uart5 special mode register 2 u5smr2 00h 0001c7h uart5 special mode register u5smr 00h 0001c8h uart5 transmit/receive mode register u5mr 00h 0001c9h uart5 bit ra te register u5brg xxh 0001cah uart5 transmit buffer register u5tb xxxxh 0001cbh 0001cch uart5 transmit/receive control register 0 u5c0 0000 1000b 0001cdh uart5 transmit/receive control register 1 u5c1 0000 0010b 0001ceh uart5 receive buffer register u5rb xxxxh 0001cfh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 45 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.10 sfr list (10) address register symbol reset value 0001d0h 0001d1h 0001d2h 0001d3h 0001d4h uart6 special mode register 4 u6smr4 00h 0001d5h uart6 special mode register 3 u6smr3 00h 0001d6h uart6 special mode register 2 u6smr2 00h 0001d7h uart6 special mode register u6smr 00h 0001d8h uart6 transmit/receive mode register u6mr 00h 0001d9h uart6 bit ra te register u6brg xxh 0001dah uart6 transmit buffer register u6tb xxxxh 0001dbh 0001dch uart6 transmit/receive control register 0 u6c0 0000 1000b 0001ddh uart6 transmit/receive control register 1 u6c1 0000 0010b 0001deh uart6 receive buffer register u6rb xxxxh 0001dfh 0001e0h uart7 transmit/receive mode register u7mr 00h 0001e1h uart7 bit rate register u7brg xxh 0001e2h uart7 transmit buffer register u7tb xxxxh 0001e3h 0001e4h uart7 transmit/receive control register 0 u7c0 00x0 1000b 0001e5h uart7 transmit/receive control register 1 u7c1 xxxx 0010b 0001e6h uart7 receive buffer register u7rb xxxxh 0001e7h 0001e8h uart8 transmit/receive mode register u8mr 00h 0001e9h uart8 bit rate register u8brg xxh 0001eah uart8 transmit buffer register u8tb xxxxh 0001ebh 0001ech uart8 transmit/receive control register 0 u8c0 00x0 1000b 0001edh uart8 transmit/receive co ntrol register 1 u8c1 xxxx 0010b 0001eeh uart8 receive buffer register u8rb xxxxh 0001efh 0001f0h uart7, uart8 transmit/receive control register 2 u78con x000 0000b 0001f1h 0001f2h 0001f3h 0001f4h 0001f5h 0001f6h 0001f7h 0001f8h 0001f9h 0001fah 0001fbh 0001fch 0001fdh 0001feh 0001ffh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 46 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.11 sfr list (11) address register symbol reset value 000200h to 0002bfh 0002c0h x0 register/y 0 register x0r/y0r xxxxh 0002c1h 0002c2h x1 register/y 1 register x1r/y1r xxxxh 0002c3h 0002c4h x2 register/y 2 register x2r/y2r xxxxh 0002c5h 0002c6h x3 register/y 3 register x3r/y3r xxxxh 0002c7h 0002c8h x4 register/y 4 register x4r/y4r xxxxh 0002c9h 0002cah x5 register/y 5 register x5r/y5r xxxxh 0002cbh 0002cch x6 register/y6 register x6r/y6r xxxxh 0002cdh 0002ceh x7 register/y 7 register x7r/y7r xxxxh 0002cfh 0002d0h x8 register/y 8 register x8r/y8r xxxxh 0002d1h 0002d2h x9 register/y 9 register x9r/y9r xxxxh 0002d3h 0002d4h x10 register/y10 register x10r/y10r xxxxh 0002d5h 0002d6h x11 register/y11 register x11r/y11r xxxxh 0002d7h 0002d8h x12 register/y12 register x12r/y12r xxxxh 0002d9h 0002dah x13 register/y13 register x13r/y13r xxxxh 0002dbh 0002dch x14 register/y14 register x14r/y14r xxxxh 0002ddh 0002deh x15 register/y15 register x15r/y15r xxxxh 0002dfh 0002e0h x-y control register xyc xxxx xx00b 0002e1h 0002e2h 0002e3h 0002e4h uart1 special mode register 4 u1smr4 00h 0002e5h uart1 special mode register 3 u1smr3 00h 0002e6h uart1 special mode register 2 u1smr2 00h 0002e7h uart1 special mode register u1smr 00h 0002e8h uart1 transmit/receive mode register u1mr 00h 0002e9h uart1 bit rate register u1brg xxh 0002eah uart1 transmit buffer register u1tb xxxxh 0002ebh 0002ech uart1 transmit/receive control register 0 u1c0 0000 1000b 0002edh uart1 transmit/receive control register 1 u1c1 0000 0010b 0002eeh uart1 receive buffer register u1rb xxxxh 0002efh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 47 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.12 sfr list (12) address register symbol reset value 0002f0h 0002f1h 0002f2h 0002f3h 0002f4h uart4 special mode register 4 u4smr4 00h 0002f5h uart4 special mode register 3 u4smr3 00h 0002f6h uart4 special mode register 2 u4smr2 00h 0002f7h uart4 special mode register u4smr 00h 0002f8h uart4 transmit/receive mode register u4mr 00h 0002f9h uart4 bit rate register u4brg xxh 0002fah uart4 transmit buffer register u4tb xxxxh 0002fbh 0002fch uart4 transmit/receive control register 0 u4c0 0000 1000b 0002fdh uart4 transmit/receive control register 1 u4c1 0000 0010b 0002feh uart4 receive buffer register u4rb xxxxh 0002ffh 000300h count start register for timers b3, b4, and b5 tbsr 000x xxxxb 000301h 000302h timer a1-1 register ta11 xxxxh 000303h 000304h timer a2-1 register ta21 xxxxh 000305h 000306h timer a4-1 register ta41 xxxxh 000307h 000308h three-phase pwm control register 0 invc0 00h 000309h three-phase pwm control register 1 invc1 00h 00030ah three-phase output buffer register 0 idb0 xx11 1111b 00030bh three-phase output buffer register 1 idb1 xx11 1111b 00030ch dead time timer dtt xxh 00030dh timer b2 interrupt generating frequency set counter ictb2 xxh 00030eh 00030fh 000310h timer b3 register tb3 xxxxh 000311h 000312h timer b4 register tb4 xxxxh 000313h 000314h timer b5 register tb5 xxxxh 000315h 000316h 000317h 000318h 000319h 00031ah 00031bh timer b3 mode register tb3mr 00xx 0000b 00031ch timer b4 mode register tb4mr 00xx 0000b 00031dh timer b5 mode register tb5mr 00xx 0000b 00031eh 00031fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 48 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.13 sfr list (13) address register symbol reset value 000320h 000321h 000322h 000323h 000324h uart3 special mode register 4 u3smr4 00h 000325h uart3 special mode register 3 u3smr3 00h 000326h uart3 special mode register 2 u3smr2 00h 000327h uart3 special mode register u3smr 00h 000328h uart3 transmit/receive mode register u3mr 00h 000329h uart3 bit rate register u3brg xxh 00032ah uart3 transmit buffer register u3tb xxxxh 00032bh 00032ch uart3 transmit/receive control register 0 u3c0 0000 1000b 00032dh uart3 transmit/receive control register 1 u3c1 0000 0010b 00032eh uart3 receive buffer register u3rb xxxxh 00032fh 000330h 000331h 000332h 000333h 000334h uart2 special mode register 4 u2smr4 00h 000335h uart2 special mode register 3 u2smr3 00h 000336h uart2 special mode register 2 u2smr2 00h 000337h uart2 special mode register u2smr 00h 000338h uart2 transmit/receive mode register u2mr 00h 000339h uart2 bit rate register u2brg xxh 00033ah uart2 transmit buffer register u2tb xxxxh 00033bh 00033ch uart2 transmit/receive control register 0 u2c0 0000 1000b 00033dh uart2 transmit/receive control register 1 u2c1 0000 0010b 00033eh uart2 receive buffer register u2rb xxxxh 00033fh 000340h count start register tabsr 0000 0000b 000341h clock prescaler reset register cpsrf 0xxx xxxxb 000342h one-shot start register onsf 0000 0000b 000343h trigger select register trgsr 0000 0000b 000344h increment/decrement select register udf 0000 0000b 000345h 000346h timer a0 register ta0 xxxxh 000347h 000348h timer a1 register ta1 xxxxh 000349h 00034ah timer a2 register ta2 xxxxh 00034bh 00034ch timer a3 register ta3 xxxxh 00034dh 00034eh timer a4 register ta4 xxxxh 00034fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 49 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.14 sfr list (14) address register symbol reset value 000350h timer b0 register tb0 xxxxh 000351h 000352h timer b1 register tb1 xxxxh 000353h 000354h timer b2 register tb2 xxxxh 000355h 000356h timer a0 mode register ta0mr 0000 0000b 000357h timer a1 mode register ta1mr 0000 0000b 000358h timer a2 mode register ta2mr 0000 0000b 000359h timer a3 mode register ta3mr 0000 0000b 00035ah timer a4 mode register ta4mr 0000 0000b 00035bh timer b0 mode register tb0mr 00xx 0000b 00035ch timer b1 mode register tb1mr 00xx 0000b 00035dh timer b2 mode register tb2mr 00xx 0000b 00035eh timer b2 special mode register tb2sc xxxx xxx0b 00035fh count source prescaler register tcspr 0000 0000b 000360h 000361h 000362h 000363h 000364h uart0 special mode register 4 u0smr4 00h 000365h uart0 special mode register 3 u0smr3 00h 000366h uart0 special mode register 2 u0smr2 00h 000367h uart0 special mode register u0smr 00h 000368h uart0 transmit/receive mode register u0mr 00h 000369h uart0 bit rate register u0brg xxh 00036ah uart0 transmit buffer register u0tb xxxxh 00036bh 00036ch uart0 transmit/receive control register 0 u0c0 0000 1000b 00036dh uart0 transmit/receive control register 1 u0c1 0000 0010b 00036eh uart0 receive buffer register u0rb xxxxh 00036fh 000370h 000371h 000372h 000373h 000374h 000375h 000376h 000377h 000378h 000379h 00037ah 00037bh 00037ch crc data register crcd xxxxh 00037dh 00037eh crc input register crcin xxh 00037fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 50 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.15 sfr list (15) address register symbol reset value 000380h a/d0 register 0 ad00 00xxh 000381h 000382h a/d0 register 1 ad01 00xxh 000383h 000384h a/d0 register 2 ad02 00xxh 000385h 000386h a/d0 register 3 ad03 00xxh 000387h 000388h a/d0 register 4 ad04 00xxh 000389h 00038ah a/d0 register 5 ad05 00xxh 00038bh 00038ch a/d0 register 6 ad06 00xxh 00038dh 00038eh a/d0 register 7 ad07 00xxh 00038fh 000390h 000391h 000392h a/d0 control register 4 ad0con4 xxxx 00xxb 000393h 000394h a/d0 control register 2 ad0con2 xx0x x000b 000395h a/d0 control register 3 ad0con3 xxxx x000b 000396h a/d0 control register 0 ad0con0 00h 000397h a/d0 control register 1 ad0con1 00h 000398h d/a register 0 da0 xxh 000399h 00039ah d/a register 1 da1 xxh 00039bh 00039ch d/a control register dacon xxxx xx00b 00039dh 00039eh 00039fh 0003a0h 0003a1h 0003a2h 0003a3h 0003a4h 0003a5h 0003a6h 0003a7h 0003a8h 0003a9h 0003aah 0003abh 0003ach 0003adh 0003aeh 0003afh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 51 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.16 sfr list (16) address register symbol reset value 0003b0h 0003b1h 0003b2h 0003b3h 0003b4h 0003b5h 0003b6h 0003b7h 0003b8h 0003b9h 0003bah 0003bbh 0003bch 0003bdh 0003beh 0003bfh 0003c0h port p0 register p0 xxh 0003c1h port p1 register p1 xxh 0003c2h port p0 direction register pd0 0000 0000b 0003c3h port p1 direction register pd1 0000 0000b 0003c4h port p2 register p2 xxh 0003c5h port p3 register p3 xxh 0003c6h port p2 direction register pd2 0000 0000b 0003c7h port p3 direction register pd3 0000 0000b 0003c8h port p4 register p4 xxh 0003c9h port p5 register p5 xxh 0003cah port p4 direction register pd4 0000 0000b 0003cbh port p5 direction register pd5 0000 0000b 0003cch port p6 register p6 xxh 0003cdh port p7 register p7 xxh 0003ceh port p6 direction register pd6 0000 0000b 0003cfh port p7 direction register pd7 0000 0000b 0003d0h port p8 register p8 xxh 0003d1h port p9 register p9 xxh 0003d2h port p8 direction register pd8 00x0 0000b 0003d3h port p9 direction register pd9 0000 0000b 0003d4h port p10 register p10 xxh 0003d5h 0003d6h port p10 direction register pd10 0000 0000b 0003d7h 0003d8h 0003d9h 0003dah 0003dbh 0003dch 0003ddh 0003deh 0003dfh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 52 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.17 sfr list (17) address register symbol reset value 0003e0h 0003e1h 0003e2h 0003e3h 0003e4h 0003e5h 0003e6h 0003e7h 0003e8h 0003e9h 0003eah 0003ebh 0003ech 0003edh 0003eeh 0003efh 0003f0h pull-up control register 0 pur0 0000 0000b 0003f1h pull-up control register 1 pur1 xxxx 0000b 0003f2h pull-up control register 2 pur2 0000 0000b 0003f3h pull-up control register 3 pur3 xxxx xx00b 0003f4h 0003f5h 0003f6h 0003f7h 0003f8h 0003f9h 0003fah 0003fbh 0003fch 0003fdh 0003feh 0003ffh port control register pcr xxxx xxx0b x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 53 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) note: 1. the reset value reflects the value of the protect bit for each block in the flash memory. table 4.18 sfr list (18) address register symbol reset value 040000h flash memory control register 0 fmr0 0x01 xx00b 040001h flash memory status register 0 fmsr0 1000 0000b 040002h 040003h 040004h 040005h 040006h 040007h 040008h flash register protection unlock register 0 fpr0 00h 040009h flash memory control register 1 fmr1 0000 0010b 04000ah block protect bit monitor register 0 fbpm0 ??x? ????b (1) 04000bh block protect bit monitor register 1 fbpm1 xxx? ????b (1) 04000ch 04000dh 04000eh 04000fh 040010h 040011h 040012h 040013h 040014h 040015h 040016h 040017h 040018h 040019h 04001ah 04001bh 04001ch 04001dh 04001eh 04001fh 040020h pll control register 0 plc0 0000 0001b 040021h pll control register 1 plc1 0001 1111b 040022h 040023h 040024h 040025h 040026h 040027h 040028h 040029h 04002ah 04002bh 04002ch 04002dh 04002eh 04002fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 54 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) note: 1. the value in the pm0 register is retained even after a software reset or watchdog timer reset. table 4.19 sfr list (19) address register symbol reset value 040030h to 04003fh 040040h 040041h 040042h 040043h 040044h processor mode register 0 (1) pm0 1000 0000b (cnvss pin = low) 0000 0011b (cnvss pin = high) 040045h 040046h system clock control register 0 cm0 0000 1000b 040047h system clock control register 1 cm1 0010 0000b 040048h processor mode register 3 pm3 00h 040049h 04004ah protect register prcr xxxx x000b 04004bh 04004ch protect register 3 prcr3 0000 0000b 04004dh oscillator stop detection register cm2 00h 04004eh 04004fh 040050h 040051h 040052h 040053h processor mode register 2 pm2 00h 040054h chip select output pin setting register 0 csop0 1000 xxxxb 040055h chip select output pin setting register 1 csop1 01x0 xxxxb 040056h 040057h 040058h 040059h 04005ah low speed mode clock control register cm3 xxxx xx00b 04005bh 04005ch 04005dh 04005eh 04005fh 040060h voltage regulator control register vrcr 0000 0000b 040061h 040062h low voltage detector control register lvdc 0000 xx00b 040063h 040064h detection voltage configuration register dvcr 0000 xxxxb 040065h 040066h 040067h 040068h to 040093h x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 55 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) notes: 1. the reset value is 0000 0000b in the 80-/64-pin package. 2. the reset value is 0000 000xb in the 80-/64-pin package. 3. this register is provided for the 80-64/pin pack age. no access is allowe d in the 100-pin package. table 4.20 sfr list (20) address register symbol reset value 040094h 040095h 040096h 040097h three-phase output buffer control register iobc 0xxx xxxxb 040098h input function select register 0 ifs0 x000 0000b (1) 040099h 04009ah input function select register 2 ifs2 0000 00x0b (2) 04009bh input function select register 3 ifs3 xxxx xx00b 04009ch 04009dh 04009eh 04009fh input function select register 7 (3) ifs7 xxxx xx0xb 0400a0h port p0_0 function select register p0_0s 0xxx x000b 0400a1h port p1_0 function select register p1_0s xxxx x000b 0400a2h port p0_1 function select register p0_1s 0xxx x000b 0400a3h port p1_1 function select register p1_1s xxxx x000b 0400a4h port p0_2 function select register p0_2s 0xxx x000b 0400a5h port p1_2 function select register p1_2s xxxx x000b 0400a6h port p0_3 function select register p0_3s 0xxx x000b 0400a7h port p1_3 function select register p1_3s xxxx x000b 0400a8h port p0_4 function select register p0_4s 0xxx x000b 0400a9h port p1_4 function select register p1_4s xxxx x000b 0400aah port p0_5 function sele ct register p0_5s 0xxx x000b 0400abh port p1_5 function se lect register p1_5s xxxx x000b 0400ach port p0_6 function select register p0_6s 0xxx x000b 0400adh port p1_6 function se lect register p1_6s xxxx x000b 0400aeh port p0_7 function sele ct register p0_7s 0xxx x000b 0400afh port p1_7 function se lect register p1_7s xxxx x000b 0400b0h port p2_0 function select register p2_0s 0xxx x000b 0400b1h port p3_0 function select register p3_0s xxxx x000b 0400b2h port p2_1 function select register p2_1s 0xxx x000b 0400b3h port p3_1 function select register p3_1s xxxx x000b 0400b4h port p2_2 function select register p2_2s 0xxx x000b 0400b5h port p3_2 function select register p3_2s xxxx x000b 0400b6h port p2_3 function select register p2_3s 0xxx x000b 0400b7h port p3_3 function select register p3_3s xxxx x000b 0400b8h port p2_4 function select register p2_4s 0xxx x000b 0400b9h port p3_4 function select register p3_4s xxxx x000b 0400bah port p2_5 function sele ct register p2_5s 0xxx x000b 0400bbh port p3_5 function se lect register p3_5s xxxx x000b 0400bch port p2_6 function select register p2_6s 0xxx x000b 0400bdh port p3_6 function se lect register p3_6s xxxx x000b 0400beh port p2_7 function sele ct register p2_7s 0xxx x000b 0400bfh port p3_7 function se lect register p3_7s xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 56 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.21 sfr list (21) address register symbol reset value 0400c0h port p4_0 function se lect register p4_0s xxxx x000b 0400c1h port p5_0 function se lect register p5_0s xxxx x000b 0400c2h port p4_1 function se lect register p4_1s xxxx x000b 0400c3h port p5_1 function se lect register p5_1s xxxx x000b 0400c4h port p4_2 function se lect register p4_2s xxxx x000b 0400c5h port p5_2 function se lect register p5_2s xxxx x000b 0400c6h port p4_3 function se lect register p4_3s xxxx x000b 0400c7h port p5_3 function se lect register p5_3s xxxx x000b 0400c8h port p4_4 function se lect register p4_4s xxxx x000b 0400c9h port p5_4 function se lect register p5_4s xxxx x000b 0400cah port p4_5 function se lect register p4_5s xxxx x000b 0400cbh port p5_5 function se lect register p5_5s xxxx x000b 0400cch port p4_6 function select register p4_6s xxxx x000b 0400cdh port p5_6 function select register p5_6s xxxx x000b 0400ceh port p4_7 function se lect register p4_7s xxxx x000b 0400cfh port p5_7 function se lect register p5_7s xxxx x000b 0400d0h port p6_0 function se lect register p6_0s xxxx x000b 0400d1h port p7_0 function se lect register p7_0s xxxx x000b 0400d2h port p6_1 function se lect register p6_1s xxxx x000b 0400d3h port p7_1 function se lect register p7_1s xxxx x000b 0400d4h port p6_2 function se lect register p6_2s xxxx x000b 0400d5h port p7_2 function se lect register p7_2s xxxx x000b 0400d6h port p6_3 function se lect register p6_3s xxxx x000b 0400d7h port p7_3 function se lect register p7_3s xxxx x000b 0400d8h port p6_4 function se lect register p6_4s xxxx x000b 0400d9h port p7_4 function se lect register p7_4s xxxx x000b 0400dah port p6_5 function se lect register p6_5s xxxx x000b 0400dbh port p7_5 function se lect register p7_5s xxxx x000b 0400dch port p6_6 function select register p6_6s xxxx x000b 0400ddh port p7_6 function select register p7_6s xxxx x000b 0400deh port p6_7 function se lect register p6_7s xxxx x000b 0400dfh port p7_7 function se lect register p7_7s xxxx x000b 0400e0h port p8_0 function select register p8_0s xxxx x000b 0400e1h 0400e2h port p8_1 function select register p8_1s xxxx x000b 0400e3h 0400e4h port p8_2 function select register p8_2s xxxx x000b 0400e5h 0400e6h port p8_3 function select register p8_3s xxxx x000b 0400e7h port p9_3 function select register p9_3s 0xxx x000b 0400e8h port p8_4 function select register p8_4s xxxx x000b 0400e9h port p9_4 function select register p9_4s 0xxx x000b 0400eah 0400ebh port p9_5 function se lect register p9_5s 0xxx x000b 0400ech port p8_6 function se lect register p8_6s xxxx x000b 0400edh port p9_6 function se lect register p9_6s 0xxx x000b 0400eeh port p8_7 function se lect register p8_7s xxxx x000b 0400efh port p9_7 function se lect register p9_7s xxxx x000b x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 57 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.22 sfr list (22) address register symbol reset value 0400f0h port p10_0 function select register p10_0s 0xxx x000b 0400f1h 0400f2h port p10_1 function select register p10_1s 0xxx x000b 0400f3h 0400f4h port p10_2 function select register p10_2s 0xxx x000b 0400f5h 0400f6h port p10_3 function select register p10_3s 0xxx x000b 0400f7h 0400f8h port p10_4 function select register p10_4s 0xxx x000b 0400f9h 0400fah port p10_5 function select register p10_5s 0xxx x000b 0400fbh 0400fch port p10_6 function select register p10_6s 0xxx x000b 0400fdh 0400feh port p10_7 function select register p10_7s 0xxx x000b 0400ffh 040100h 040101h 040102h 040103h 040104h 040105h 040106h 040107h 040108h 040109h 04010ah 04010bh 04010ch 04010dh 04010eh 04010fh 040110h 040111h 040112h 040113h 040114h 040115h 040116h 040117h 040118h 040119h 04011ah 04011bh 04011ch 04011dh 04011eh 04011fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 58 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.23 sfr list (23) address register symbol reset value 040120h to 04403fh 044040h 044041h 044042h 044043h 044044h 044045h 044046h 044047h 044048h 044049h 04404ah 04404bh 04404ch 04404dh 04404eh watchdog timer start register wdts xxxx xxxxb 04404fh watchdog timer control register wdc 000x xxxxb 044050h 044051h 044052h 044053h 044054h 044055h 044056h 044057h 044058h 044059h 04405ah 04405bh 04405ch 04405dh 04405eh 04405fh protect register 2 prcr2 0xxx xxxxb x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 59 of 99 sep 26, 2011 r32c/111 group 4. special function registers (sfrs) table 4.24 sfr list (24) address register symbol reset value 044060h 044061h 044062h 044063h 044064h 044065h 044066h 044067h 044068h 044069h 04406ah 04406bh 04406ch 04406dh external interrupt request source select re gister 1 ifsr1 x0xx xxxxb 04406eh 04406fh external interrupt request source select register 0 ifsr0 0000 0000b 044070h dma0 request source select register 2 dm0sl2 xx00 0000b 044071h dma1 request source select register 2 dm1sl2 xx00 0000b 044072h dma2 request source select register 2 dm2sl2 xx00 0000b 044073h dma3 request source select register 2 dm3sl2 xx00 0000b 044074h 044075h 044076h 044077h 044078h dma0 request source select register dm0sl xxx0 0000b 044079h dma1 request source select register dm1sl xxx0 0000b 04407ah dma2 request source select register dm2sl xxx0 0000b 04407bh dma3 request source select register dm3sl xxx0 0000b 04407ch 04407dh wake-up ipl setting register 2 ripl2 xx0x 0000b 04407eh 04407fh wake-up ipl setting register 1 ripl1 xx0x 0000b 044080h 044081h 044082h 044083h 044084h 044085h 044086h 044087h 044088h 044089h 04408ah 04408bh 04408ch 04408dh 04408eh 04408fh x: undefined blanks are reserved. no access is allowed.
r01ds0062ej0120 rev.1.20 page 60 of 99 sep 26, 2011 r32c/111 group 5. ele ctrical characteristics 5. electrical characteristics notes: 1. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ra ting conditions for ex tended periods may affe ct device reliability. 2. the v cc2 pin is available in the 100-pin package only. it should be considered as v cc1 in the 80-/64- pin package. 3. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 100- and 80-pin packages. ports p4, p5, p9_1, and p9_4 are available in the 100-pin package only. table 5.1 absolute maximum ratings (1) symbol characteristic condition value (2) unit v cc1, v cc2 supply voltage v cc1 = av cc -0.3 to 6.0 v v cc2 supply voltage ? -0.3 to v cc1 v av cc analog supply voltage v cc1 = av cc -0.3 to 6.0 v v i input voltage xin, reset , cnvss, nsd, v ref , p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 (3) -0.3 to v cc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 (3) -0.3 to v cc2 + 0.3 v p7_0, p7_1 -0.3 to 6.0 v v o output voltage xout, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (3) -0.3 to v cc1 + 0.3 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 (3) -0.3 to v cc2 + 0.3 v p7_0, p7_1 -0.3 to 6.0 v p d power consumption t a = 25c 500 mw ? operating temperature range -40 to 85 c t stg storage temperature range -65 to 150 c
r01ds0062ej0120 rev.1.20 page 61 of 99 sep 26, 2011 r32c/111 group 5. ele ctrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. the v cc2 pin is available in the 100-pin package only. it should be considered as v cc1 in the 80-/64- pin package. 3. v ih and v il for p8_7 are specified for p8_7 as a programmable port. these values are not applicable for p8_7 as xcin. 4. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 100- and 80-pin packages. ports p4, p5, p9_1, and p9_4 are available in the 100-pin package only. 5. memory expansion mode and microprocessor mode are available in the 100-pin package only. table 5.2 operating conditions (1/5) (1) symbol characteristic value (2) unit min. typ. max. v cc1, v cc2 digital supply voltage (v cc1 v cc2 ) 3.0 5.0 5.5 v av cc analog supply voltage v cc1 v v ref reference voltage 3.0 v cc1 v v ss digital ground voltage 0v av ss analog ground voltage 0v dv cc1 / dt v cc1 ramp up rate (v cc1 < 2.0 v) 0.05 v/ms v ih high level input voltage p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 (4) 0.8 v cc2 v cc2 v xin, reset , cnvss, nsd, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_7 (3) , p9_1, p9_3 to p9_7, p10_0 to p10_7 (4) 0.8 v cc1 v cc1 v p7_0, p7_1 0.8 v cc1 6.0 v p0_0 to p0_7, p1_0 to p1_7 (4) in single-chip mode 0.8 v cc2 v cc2 v in memory expansion mode or microprocessor mode (5) 0.5 v cc2 v cc2 v v il low level input voltage p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 (4) 0 0.2 v cc2 v xin, reset , cnvss, nsd, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7 (3) , p9_1, p9_3 to p9_7, p10_0 to p10_7 (4) 0 0.2 v cc1 v p0_0 to p0_7, p1_0 to p1_7 (4) in single-chip mode 0 0.2 v cc2 v in memory expansion mode or microprocessor mode (5) 0 0.16 v cc2 v t opr operating temperature range n version -20 85 c d version -40 85 c
r01ds0062ej0120 rev.1.20 page 62 of 99 sep 26, 2011 r32c/111 group 5. ele ctrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. this value should be met with due consideration to the following conditions: operating temperature, dc bias, aging, etc. table 5.3 operating conditions (2/5) (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value (2) unit min. typ. max. c vdc decoupling capacitance for voltage regulator inter-pin voltage: 1.5 v 2.4 10.0 f
r01ds0062ej0120 rev.1.20 page 63 of 99 sep 26, 2011 r32c/111 group 5. ele ctrical characteristics notes: 1. the device is operationally guaranteed under these operating conditions. 2. the following conditions should be satisfied: ? the sum of i ol(peak) of ports p0, p1, p2, p8_6, p8_7, p9, and p10 is 80 ma or less. ? the sum of i ol(peak) of ports p3, p4, p5, p6, p7, an d p8_0 to p8_4 is 80 ma or less. ? the sum of i oh(peak) of ports p0, p1, and p2 is -40 ma or less. ? the sum of i oh(peak) of ports p8_6, p8_7, p9, and p10 is -40 ma or less. ? the sum of i oh(peak) of ports p3, p4, and p5 is -40 ma or less. ? the sum of i oh(peak) of ports p6, p7, and p8_0 to p8_4 is -40 ma or less. 3. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 100- and 80-pin packages. ports p4, p5, and p9_4 are available in the 100-pin package only. 4. average value within 100 ms. table 5.4 operating conditions (3/5) (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. i oh (peak) high level peak output current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (3) -10.0 ma i oh (avg) high level average output current (4) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (3) -5.0 ma i ol (peak) low level peak output current (2) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (3) 10.0 ma i ol (avg) low level average output current (4) p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (3) 5.0 ma
r01ds0062ej0120 rev.1.20 page 64 of 99 sep 26, 2011 r32c/111 group 5. ele ctrical characteristics note: 1. the device is operationally guaranteed under these operating conditions. figure 5.1 clock cycle time table 5.5 operating conditions (4/5) (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. f (xin) main clock osc illator frequency 416mhz f (xref) reference clock frequency 24mhz f (pll) pll clock oscilla tor frequency 96 128 mhz f (base) base clock frequency 50 mhz t c(base) base clock cycle time 20 ns f (cpu) cpu operating frequency 50 mhz t c (cpu) cpu clock cycle time 20 ns f (bclk) peripheral bus clock operating frequency 25 mhz t c (bclk) peripheral bus clock cycle time 40 ns f (per) peripheral clock source frequency 32 mhz f (xcin) sub clock oscillator frequency 32.768 62.5 khz base clock (internal signal) t c(base) peripheral bus clock (internal signal) t c(bclk) cpu clock (internal signal) t c(cpu)
r01ds0062ej0120 rev.1.20 page 65 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics note: 1. the device is operationally guaranteed under these operating conditions. figure 5.2 ripple waveform table 5.6 operating conditions (5/5) (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) (1) symbol characteristic value unit min. typ. max. v r(vcc1) allowable ripple voltage v cc1 = 5.0 v 0.5 vp-p v cc1 = 3.0 v 0.3 vp-p v r(vcc2) allowable ripple voltage v cc2 = 5.0 v 0.5 vp-p v cc2 = 3.0 v 0.3 vp-p dv r(vcc1) /dt ripple voltage gradient v cc1 = 5.0 v 0.3 v/ms v cc1 = 3.0 v 0.3 v/ms dv r(vcc2) /dt ripple voltage gradient v cc2 = 5.0 v 0.3 v/ms v cc2 = 3.0 v 0.3 v/ms f r(vcc1) allowable ripple frequency 10 khz f r(vcc2) allowable ripple frequency 10 khz or 1 / f r(vcc1) v r(vcc1) 1 / f r(vcc2) v r(vcc2) or or v cc1 v cc2
r01ds0062ej0120 rev.1.20 page 66 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics note: 1. the value listed in the table is the minimum v cc1 to retain ram data. notes: 1. program/erase definition this value represents the number of erasures per block. when the number of program and erase cycles is n, each block can be erased n times. for example, if a 4-word write is performed in 512 different addresses in the 4-kbyte block a and then the block is erased, this is counted as a single program/erase operation. however, the same address cannot be written to more than once per erasure (overwrite disabled). 2. data retention includes periods when no supply voltage is applied and no clock is provided. 3. contact a renesas electronics sales office for da ta retention times other than the above condition. table 5.7 electrical characteristics of ram (v cc1 =v cc2 = 3.0 to 5.5 v, v ss = 0 v, and ta = t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v rdr ram data retention voltage (1) in stop mode 2.0 v table 5.8 electrical charac teristics of flash memory (v cc1 = v cc2 = 3.0 to 5.5 v, v ss = 0 v, and ta = t opr , unless otherwise noted) symbol characteristic value unit min. typ. max. ? program and erase cycles (1) program area 1000 cycles data area 10000 cycles ? 4-word program time program area 150 900 s data area 300 1700 s ? lock bit-program time program area 70 500 s data area 140 1000 s ? block erasure time 4-kbyte block 0.12 3.0 s 32-kbyte block 0.17 3.0 s 64-kbyte block 0.20 3.0 s ? data retention (2) t a = 55c (3) 10 years
r01ds0062ej0120 rev.1.20 page 67 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics figure 5.3 power supply circuit timing table 5.9 power supply circ uit timing characteristics (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. t d(p-r) internal power supply start-up stabilization time after the main power supply is turned on 2ms table 5.10 electrical charac teristics of voltage regu lator for internal logic (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. v vdc1 output voltage 1.5 v table 5.11 electrical characteri stics of low voltage detector (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. vdet detected voltage error 0.3 v vdet(r)-vdet(f) hysteresis width 0 v ? self-consuming current v cc1 = 5.0 v, low voltage detector enabled 4a t d(e-a) operation start time of low voltage detector 150 s t d(p-r) v cc1 pll oscillator- output waveform internal power supply start-up stabilization time after the main power supply is turned on recommended operating voltage t d(p-r) supply voltage for internal logic
r01ds0062ej0120 rev.1.20 page 68 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics note: 1. this value is applicable only when the main clock osc illation is stable. note: 1. the stop mode reco very time does not inclu de the main clock oscillation stabilization time. the cpu starts operating before th e oscillator is stabilized. figure 5.4 clock circuit timing table 5.12 electrical char acteristics of oscillator (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. f so(pll) pll clock self-osc illation frequency 35 55 80 mhz t lock(pll) pll lock time (1) 1ms t jitter(p-p) pll jitter period (p-p) 2.0 ns f (oco) on-chip oscillator frequency 62.5 125 250 khz table 5.13 electrical characte ristics of clock circuitry (v cc1 =v cc2 = 3.0 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characteristics measurement condition value unit min. typ. max. t rec(wait) recovery time from wait mode to low power mode 225 s t rec(stop) recovery time from stop mode (1) 225 s t rec(stop) interrupt for exiting stop mode cpu clock main clock oscillator output on-chip oscillator output sub clock oscillator output on-chip oscillator output t rec(wait) interrupt for exiting wait mode cpu clock recovery time from stop mode t rec(stop) recovery time from wait mode to low power mode t rec(wait)
r01ds0062ej0120 rev.1.20 page 69 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics timing requirements (v cc1 = v cc2 = 3.0 to 5.5 v, v ss =0v, and ta=t opr , unless otherwise noted) figure 5.5 flash memory cpu rewrite mode timing table 5.14 flash memory cpu rewrite mode timing symbol characteristics value unit min. max. t cr read cycle time 200 ns t su(s-r) chip-select setup time before read 200 ns t h(r-s) chip-select hold time after read 0ns t su(a-r) address setup time before read 200 ns t h(r-a) address hold time after read 0ns t w(r) read pulse width 100 ns t cw write cycle time 200 ns t su(s-w) chip-select setup time before write 0ns t h(w-s) chip-select hold time after write 30 ns t su(a-w) address setup time before write 0ns t h(w-a) address hold time after write 30 ns t w(w) write pulse width 50 ns chip select address rd t h(r-s) read cycle t w(r) t su(s-r) t h(r-a) t su(a-r) write cycle chip select address wr t h(w-s) t w(w) t su(s-w) t h(w-a) t su(a-w) t cw t cr
r01ds0062ej0120 rev.1.20 page 70 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v notes: 1. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 100- and 80-pin packages. ports p4, p5, and p9_4 are available in the 100-pin package only. 2. the v cc2 pin is available in the 100-pin package only. it should be considered as v cc1 in the 80-/64- pin package. table 5.15 electrical characteristics (1/3) (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value (2) unit min. typ. max. v oh high level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 (1) i oh = -5 ma v cc2 -2.0 v cc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (1) i oh = -5 ma v cc1 -2.0 v cc1 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 (1) i oh = -200 a v cc2 -0.3 v cc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (1) i oh = -200 a v cc1 -0.3 v cc1 v v ol low level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (1) i ol = 5 ma 2.0 v p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (1) i ol = 200 a 0.45 v
r01ds0062ej0120 rev.1.20 page 71 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v notes: 1. pins clk4, rxd4, txd4, sda4, scl4, stxd4, and srxd4 are available in the 100- and 80-pin package only. pins tb4in, cts4 , rts4 , ss4 , uart6, and uart7 are available in the 100-pin package only. 2. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 100- and 80-pin packages. ports p4, p5, p9_1, and p9_4 are available in the 100-pin package only. table 5.16 electrical characteristics (2/3) (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v t+ - v t- hysteresis hold , rdy , nmi , int0 to int5 , ki0 to ki3 , ta0in to ta4in, ta0out to ta4out, tb0in to tb5in, cts0 to cts8 , clk0 to clk8, rxd0 to rxd8, scl0 to scl6, sda0 to sda6, ss0 to ss6 , srxd0 to srxd6, adtrg , iio0_0 to iio0_7, iio1_0 to iio1_7, ud0a, ud0b, ud1a, ud1b, isclk2, isrxd2, iein (1) 0.2 1.0 v reset 0.2 1.8 v i ih high level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 (2) v i = 5 v 5.0 a i il low level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 (2) v i = 0 v -5.0 a r pullup pull-up resistor p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 (2) v i = 0 v 30 50 170 k r f xin feedback resistor xin 1.5 m r f xcin feedback resistor xcin 15 m
r01ds0062ej0120 rev.1.20 page 72 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v table 5.17 electrical characteristics (3/3) (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characterist ic measurement condition value unit min. typ. max. i cc power supply current in single-chip mode, output pins are left open and others are connected to v ss xin-xout drive power: low xcin-xcout drive power: low f (cpu) =50mhz, f (bclk) =25mhz, f (xin) =8mhz, active: xin, pll, stopped: xcin, oco 32 45 ma f (cpu) = f so(pll) /24 mhz, active: pll (self-oscillation), stopped: xin, xcin, oco 10 ma f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco 1.2 ma f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown 220 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown 230 a f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco, t a = 25c, wait mode 960 1600 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown, t a = 25c, wait mode 8140a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown, t a = 25c, wait mode 10 150 a stopped: all clocks, main regulator: shutdown, t a = 25c 570a
r01ds0062ej0120 rev.1.20 page 73 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v note: 1. pins an0_4 to an0_7, anex0, and anex1 are available in the 100- and 80-pin package only. table 5.18 a/d conversion characteristics (v cc1 =v cc2 =av cc =v ref = 4.2 to 5.5 v, v ss =av ss =0v, t a =t opr , and f (bclk) = 25 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution v ref = v cc1 10 bits ? absolute error v ref = v cc1 = v cc2 = 5 v an_0 to an_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 (1) 3 lsb external op-amp connection mode 7 lsb inl integral non-linearity error v ref = v cc1 = v cc2 = 5 v an_0 to an_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 (1) 3 lsb external op-amp connection mode 7 lsb dnl differential non-linearity error 1 lsb ?offset error 3 lsb ? gain error 3 lsb r ladder resistor ladder v ref = v cc1 420k t conv conversion time (10 bits) ad = 16 mhz, with sample and hold function 2.06 s ad = 16 mhz, without sample and hold function 3.69 s t conv conversion time (8 bits) ad = 16 mhz, with sample and hold function 1.75 s ad = 16 mhz, without sample and hold function 3.06 s t samp sampling time ad = 16 mhz 0.188 s v ia analog input voltage 0 v ref v ad operating clock frequency without sample and hold function 0.25 16 mhz with sample and hold function 1 16 mhz
r01ds0062ej0120 rev.1.20 page 74 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v note: 1. one d/a converter is used. the dai register (i = 0, 1) of the other unused converter is set to 00h. the resistor ladder for the a/d converter is not considered. even when the vcut bit in the ad0con1 register is set to 0 (v ref disconnected), i vref is supplied. table 5.19 d/a conversion characteristics (v cc1 =v cc2 =av cc =v ref = 4.2 to 5.5 v, v ss =av ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution 8bits ? absolute precision 1.0 % t s settling time 3s r o output resistance 41020k i vref reference input current (1) 1.5 ma
r01ds0062ej0120 rev.1.20 page 75 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v timing requirements (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.20 external clock input symbol characteristic value unit min. max. t c (x) external clock input period 62.5 250 ns t w(xh) external clock input high level pulse width 25 ns t w(xl) external clock input low level pulse width 25 ns t r (x) external clock input rise time 5ns t f (x) external clock input fall time 5ns t w / t c external clock input duty 40 60 % table 5.21 external bus timing symbol characteristic value unit min. max. t su (d-r) data setup time before read 40 ns t h (r-d) data hold time after read 0ns t dis (r-d) data disable time after read 0.5 t c(base) + 10 ns
r01ds0062ej0120 rev.1.20 page 76 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v timing requirements (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.22 timer a input (counting input in event counter mode) symbol characteristic value unit min. max. t c (ta) taiin input clock cycle time 200 ns t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.23 timer a input (gating input in timer mode) symbol characteristic value unit min. max. t c (ta) taiin input clock cycle time 400 ns t w (tah) taiin input high level pulse width 180 ns t w (tal) taiin input low level pulse width 180 ns table 5.24 timer a input (external trigger input in one-shot timer mode) symbol characteristic value unit min. max. t c (ta) taiin input clock cycle time 200 ns t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.25 timer a input (external trigge r input in pulse-width modulation mode) symbol characteristic value unit min. max. t w (tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.26 timer a input (increment/decrement switching input in event counter mode) symbol characteristic value unit min. max. t c (up) taiout input clock cycle time 2000 ns t w (uph) taiout input high level pulse width 1000 ns t w (upl) taiout input low level pulse width 1000 ns t su (up-tin) taiout input setup time 400 ns t h (tin-up) taiout input hold time 400 ns
r01ds0062ej0120 rev.1.20 page 77 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v timing requirements (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.27 timer b input (counting input in event counter mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time (one edge counting) 200 ns t w (tbh) tbiin input high level pulse width (one edge counting) 80 ns t w (tbl) tbiin input low level pulse width (one edge counting) 80 ns t c (tb) tbiin input clock cycle time (both edges counting) 200 ns t w (tbh) tbiin input high level pulse width (both edges counting) 80 ns t w (tbl) tbiin input low level pulse width (both edges counting) 80 ns table 5.28 timer b input (pulse period measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w (tbh) tbiin input high level pulse width 180 ns t w (tbl) tbiin input low level pulse width 180 ns table 5.29 timer b input (pulse-width measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w (tbh) tbiin input high level pulse width 180 ns t w (tbl) tbiin input low level pulse width 180 ns
r01ds0062ej0120 rev.1.20 page 78 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v timing requirements (v cc1 =v cc2 = 4.2 to 5.5 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.30 serial interface symbol characteristic value unit min. max. t c (ck) clki input clock cycle time 200 ns t w (ckh) clki input high level pulse width 80 ns t w (ckl) clki input low level pulse width 80 ns t su (d-c) rxdi input setup time 80 ns t h (c-d) rxdi input hold time 90 ns table 5.31 a/d trigger input symbol characteristic value unit min. max. t w (adh) adtrg input high level pulse width hardware trigger input high level pulse width ns t w (adl) adtrg input low level pulse width hardware trigger input high level pulse width 125 ns table 5.32 external interrupt inti input symbol characteristic value unit min. max. t w (inh) inti input high level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns t w (inl) inti input low level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns table 5.33 intelligent i/o symbol characteristic value unit min. max. t c(isclk2) isclk2 input clock cycle time 600 ns t w(isclk2h) isclk2 input high level pulse width 270 ns t w(isclk2l) isclk2 input low level pulse width 270 ns t su(rxd-isclk2) isrxd2 input setup time 150 ns t h(isclk2-rxd) isrxd2 input hold time 100 ns 3 ad --------- -
r01ds0062ej0120 rev.1.20 page 79 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v switching characteristics (v cc1 =v cc2 =4.2to5.5v, v ss =0v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated using the formulas below based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative value, modify the value to be set. for details on how to set values, refer to the user?s manual. t su(s-r) = t su(a-r) = tsu(a-r) t c(base) - 15 [ns] t w(r) = tw(r) t c(base) - 10 [ns] t su(s-w) = t su(a-w) = tsu(a-w) t c(base) - 15 [ns] t w(w) = t su(d-w) = tw(w) t c(base) - 10 [ns] table 5.34 external bus timing (separate bus) symbol characteristic measurement condition value unit min. max. t su (s-r) chip-select setup time before read refer to figure 5.6 (1) ns t h (r-s) chip-select hold time after read t c(base) - 10 ns t su (a-r) address setup time before read (1) ns t h (r-a) address hold time after read t c(base) - 10 ns t w (r) read pulse width (1) ns t su (s-w) chip-select setup time before write (1) ns t h (w-s) chip-select hold time after write 1.5 t c(base) - 10 ns t su (a-w) address setup time before write (1) ns t h (w-a) address hold time after write 1.5 t c(base) - 10 ns t w (w) write pulse width (1) ns t su (d-w) data setup time before write (1) ns t h (w-d) data hold time after write 0ns
r01ds0062ej0120 rev.1.20 page 80 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v switching characteristics (v cc1 =v cc2 =4.2to5.5v, v ss =0v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated using the formulas below based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative value, modify the value to be set. for details on how to set values, refer to the user?s manual. t su(s-ale) = t su(a-ale) = t w(ale) = (tsu(a-r) - 0.5) t c(base) -15 [ns] t w(r) = tw(r) t c(base) -10 [ns] t w(w) = t su(d-w) = tw(w) t c(base) -10 [ns] table 5.35 external bus timing (multiplexed bus) symbol characteristic measurement condition value unit min. max. t su (s-ale) chip-select setup time before ale refer to figure 5.6 (1) ns t h(r-s) chip-select hold time after read 1.5 t c(base) - 10 ns t su(a-ale) address setup time before ale (1) ns t h(ale-a) address hold time after ale 0.5 t c(base) - 5 ns t h(r-a) address hold time after read 1.5 t c(base) - 10 ns t d(ale-r) ale-read delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w(ale) ale pulse width (1) ns t dis(r-a) address disable time after read 8ns t w(r) read pulse width (1) ns t h(w-s) chip-select hold time after write 1.5 t c(base) - 10 ns t h(w-a) address hold time after write 1.5 t c(base) - 10 ns t d(ale-w) ale-write delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w(w) write pulse width (1) ns t su(d-w) data setup time before write (1) ns t h(w-d) data hold time after write 0.5 t c(base) ns
r01ds0062ej0120 rev.1.20 page 81 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =5v switching characteristics (v cc1 =v cc2 =4.2to5.5v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.36 serial interface symbol characteristic measurement condition value unit min. max. t d (c-q) txdi output delay time refer to figure 5.6 80 ns t h (c-q) txdi output hold time 0ns table 5.37 intelligent i/o symbol characteristic measurement condition value unit min. max. t d (isclk2-txd) istxd2 output delay time refer to figure 5.6 180 ns t h (isclk2-rxd) istxd2 output hold time 0ns
r01ds0062ej0120 rev.1.20 page 82 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v notes: 1. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 100- and 80-pin packages. ports p4, p5, and p9_4 are available in the 100-pin package only. 2. the v cc2 pin is available in the 100-pin package only. it should be considered as v cc1 in the 80-/64- pin package. table 5.38 electrical ch aracteristics (1/3) (v cc1 =v cc2 = 3.0 to 3.6 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value (2) unit min. typ. max. v oh high level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7 (1) i oh = -1 ma v cc2 - 0.6 v cc2 v p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (1) i oh = -1 ma v cc1 - 0.6 v cc1 v v ol low level output voltage p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_3 to p9_7, p10_0 to p10_7 (1) i ol = 1 ma 0.5 v
r01ds0062ej0120 rev.1.20 page 83 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v notes: 1. pins clk4, rxd4, txd4, sda4, scl4, stxd4, and srxd4 are available in the 100- and 80-pin package only. pins tb4in, cts4 , rts4 , ss4 , uart6, and uart7 are available in the 100-pin package only. 2. ports p0_4 to p0_7, p1_0 to p1_4, p3_4 to p3_7, and p9_5 to p9_7 are available in the 100- and 80-pin packages. ports p4, p5, p9_1, and p9_4 are available in the 100-pin package only. table 5.39 electrical ch aracteristics (2/3) (v cc1 =v cc2 = 3.0 to 3.6 v, v ss =0v, t a =t opr , and f (cpu) = 50 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. v t+ - v t- hysteresis hold , rdy , nmi , int0 to int5 , ki0 to ki3 , ta0in to ta4in, ta0out to ta4out, tb0in to tb5in, cts0 to cts8 , clk0 to clk8, rxd0 to rxd8, scl0 to scl6, sda0 to sda6, ss0 to ss6 , srxd0tosrxd6, adtrg , iio0_0 to iio0_7, iio1_0 to iio1_7, ud0a, ud0b, ud1a, ud1b, isclk2, isrxd2, iein (1) 0.2 1.0 v reset 0.2 1.8 v i ih high level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 (2) v i = 3.3 v 4.0 a i il low level input current xin, reset , cnvss, nsd, p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_0 to p7_7, p8_0 to p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 (2) v i = 0 v -4.0 a r pullup pull-up resistor p0_0 to p0_7, p1_0 to p1_7, p2_0 to p2_7, p3_0 to p3_7, p4_0 to p4_7, p5_0 to p5_7, p6_0 to p6_7, p7_2 to p7_7, p8_0 to p8_4, p8_6, p8_7, p9_1, p9_3 to p9_7, p10_0 to p10_7 (2) v i = 0 v 50 100 500 k r f xin feedback resistor xin 3m r f xcin feedback resistor xcin 25 m
r01ds0062ej0120 rev.1.20 page 84 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v table 5.40 electrical characteristics (3/3) (v cc1 =v cc2 = 3.0 to 3.6 v, v ss =0v, and t a =t opr , unless otherwise noted) symbol characte ristic measurement condition value unit min. typ. max. i cc power supply current in single-chip mode, output pins are left open and others are connected to v ss xin-xout drive power: low xcin-xcout drive power: low f (cpu) =50mhz, f (bclk) =25mhz, f (xin) =8mhz, active: xin, pll, stopped: xcin, oco 28 40 ma f (cpu) = f so(pll) /24 mhz, active: pll (self-oscillation), stopped: xin, xcin, oco 7ma f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) =8mhz, active: xin, stopped: pll, xcin, oco 670 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown 180 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown 190 a f (cpu) = f (bclk) = f (xin) /256 mhz, f (xin) = 8 mhz, active: xin, stopped: pll, xcin, oco, t a = 25c, wait mode 500 900 a f (cpu) = f (bclk) = 32.768 khz, active: xcin, stopped: xin, pll, oco, main regulator: shutdown, t a = 25c, wait mode 8 140 a f (cpu) = f (bclk) = f (oco) /4 khz, active: oco, stopped: xin, pll, xcin, main regulator: shutdown, t a = 25c, wait mode 10 150 a stopped: all clocks, main regulator: shutdown, t a = 25c 570a
r01ds0062ej0120 rev.1.20 page 85 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v note: 1. pins an0_4 to an0_7, anex0, and anex1 are available in the 100- and 80-pin package only. table 5.41 a/d conversion characteristics (v cc1 =v cc2 =av cc =v ref = 3.0 to 3.6 v, v ss =av ss =0v, t a =t opr , and f (bclk) = 25 mhz, unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution v ref = v cc1 10 bits ? absolute error v ref = v cc1 = v cc2 = 3.3 v an_0 to an_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 (1) 5 lsb external op-amp connection mode 7 lsb inl integral non-linearity error v ref = v cc1 = v cc2 = 3.3 v an_0 to an_7, an0_0toan0_7, an2_0toan2_7, anex0, anex1 (1) 5 lsb external op-amp connection mode 7 lsb dnl differential non- linearity error v ref = v cc1 = v cc2 = 3.3 v 1 lsb ?offset error 3 lsb ? gain error 3 lsb r ladder resistor ladder v ref = v cc1 420k t conv conversion time (10 bits) ad = 10 mhz, with sample and hold function 3.3 s t conv conversion time (8 bits) ad = 10 mhz, with sample and hold function 2.8 s t samp sampling time ad = 10 mhz 0.3 s v ia analog input voltage 0 v ref v ad operating clock frequency without sample and hold function 0.25 10 mhz with sample and hold function 1 10 mhz
r01ds0062ej0120 rev.1.20 page 86 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v note: 1. one d/a converter is used. the dai register (i = 0, 1) of the other unused converter is set to 00h. the resistor ladder for the a/d converter is not considered. even when the vcut bit in the ad0con1 register is set to 0 (v ref disconnected), i vref is supplied. table 5.42 d/a conversion characteristics (v cc1 =v cc2 =av cc =v ref = 3.0 to 3.6 v, v ss =av ss =0v, and t a =t opr , unless otherwise noted) symbol characteristic measurement condition value unit min. typ. max. ? resolution 8bits ? absolute precision 1.0 % t s settling time 3s r o output resistance 41020k i vref reference input current (1) 1.0 ma
r01ds0062ej0120 rev.1.20 page 87 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v timing requirements (v cc1 =v cc2 = 3.0 to 3.6 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.43 external clock input symbol characteristic value unit min. max. t c (x) external clock input period 62.5 250 ns t w(xh) external clock input high level pulse width 25 ns t w(xl) external clock input low level pulse width 25 ns t r(x) external clock input rise time 5ns t f (x) external clock input fall time 5ns t w / t c external clock input duty 40 60 % table 5.44 external bus timing symbol characteristic value unit min. max. t su(d-r) data setup time before read 40 ns t h(r-d) data hold time after read 0ns t dis(r-d) data disable time after read 0.5 t c(base) + 10 ns
r01ds0062ej0120 rev.1.20 page 88 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v timing requirements (v cc1 =v cc2 = 3.0 to 3.6 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.45 timer a input (counting input in event counter mode) symbol characteristic value unit min. max. t c(ta) taiin input clock cycle time 200 ns t w(tah) taiin input high level pulse width 80 ns t w(tal) taiin input low level pulse width 80 ns table 5.46 timer a input (gating input in timer mode) symbol characteristic value unit min. max. t c(ta) taiin input clock cycle time 400 ns t w(tah) taiin input high level pulse width 180 ns t w(tal) taiin input low level pulse width 180 ns table 5.47 timer a input (external trigger input in one-shot timer mode) symbol characteristic value unit min. max. t c(ta) taiin input clock cycle time 200 ns t w(tah) taiin input high level pulse width 80 ns t w(tal) taiin input low level pulse width 80 ns table 5.48 timer a input (external trigge r input in pulse-width modulation mode) symbol characteristic value unit min. max. t w(tah) taiin input high level pulse width 80 ns t w (tal) taiin input low level pulse width 80 ns table 5.49 timer a input (increment/decrement switching input in event counter mode) symbol characteristic value unit min. max. t c(up) taiout input clock cycle time 2000 ns t w(uph) taiout input high level pulse width 1000 ns t w(upl) taiout input low level pulse width 1000 ns t su(up-tin) taiout input setup time 400 ns t h(tin-up) taiout input hold time 400 ns
r01ds0062ej0120 rev.1.20 page 89 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v timing requirements (v cc1 =v cc2 = 3.0 to 3.6 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.50 timer b input (counting input in event counter mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time (one edge counting) 200 ns t w(tbh) tbiin input high level pulse width (one edge counting) 80 ns t w(tbl) tbiin input low level pulse width (one edge counting) 80 ns t c(tb) tbiin input clock cycle time (both edges counting) 200 ns t w(tbh) tbiin input high level pulse width (both edges counting) 80 ns t w(tbl) tbiin input low level pulse width (both edges counting) 80 ns table 5.51 timer b input (pulse period measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w(tbh) tbiin input high level pulse width 180 ns t w(tbl) tbiin input low level pulse width 180 ns table 5.52 timer b input (pulse-width measure mode) symbol characteristic value unit min. max. t c(tb) tbiin input clock cycle time 400 ns t w(tbh) tbiin input high level pulse width 180 ns t w(tbl) tbiin input low level pulse width 180 ns
r01ds0062ej0120 rev.1.20 page 90 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v timing requirements (v cc1 =v cc2 = 3.0 to 3.6 v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.53 serial interface symbol characteristic value unit min. max. t c(ck) clki input clock cycle time 200 ns t w(ckh) clki input high level pulse width 80 ns t w(ckl) clki input low level pulse width 80 ns t su(d-c) rxdi input setup time 80 ns t h(c-d) rxdi input hold time 90 ns table 5.54 a/d trigger input symbol characteristic value unit min. max. t w(adh) adtrg input high level pulse width hardware trigger input high level pulse width ns t w(adl) adtrg input low level pulse width hardware trigger input high level pulse width 125 ns table 5.55 external interrupt inti input symbol characteristic value unit min. max. t w(inh) inti input high level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns t w (inl) inti input low level pulse width edge sensitive 250 ns level sensitive t c (cpu) + 200 ns table 5.56 intelligent i/o symbol characteristic value unit min. max. t c (isclk2) isclk2 input clock cycle time 600 ns t w (isclk2h) isclk2 input high level pulse width 270 ns t w (isclk2l) isclk2 input low level pulse width 270 ns t su (rxd-isclk2) isrxd2 input setup time 150 ns t h (isclk2-rxd) isrxd2 input hold time 100 ns 3 ad --------- -
r01ds0062ej0120 rev.1.20 page 91 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v switching characteristics (v cc1 =v cc2 =3.0to3.6v, v ss =0v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated using the formulas below based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative value, modify the value to be set. for details on how to set values, refer to the user?s manual. t su(s-r) = t su(a-r) = tsu(a-r) t c(base) - 15 [ns] t w(r) = tw(r) t c(base) - 10 [ns] t su(s-w) = t su(a-w) = tsu(a-w) t c(base) - 15 [ns] t w(w) = t su(d-w) = tw(w) t c(base) - 10 [ns] table 5.57 external bus timing (separate bus) symbol characteristic measurement condition value unit min. max. t su(s-r) chip-select setup time before read refer to figure 5.6 (1) ns t h(r-s) chip-select hold time after read t c(base) - 10 ns t su(a-r) address setup time before read (1) ns t h(r-a) address hold time after read t c(base) - 10 ns t w(r) read pulse width (1) ns t su(s-w) chip-select setup time before write (1) ns t h(w-s) chip-select hold time after write 1.5 t c(base) - 10 ns t su(a-w) address setup time before write (1) ns t h(w-a) address hold time after write 1.5 t c(base) - 10 ns t w(w) write pulse width (1) ns t su(d-w) data setup time before write (1) ns t h(w-d) data hold time after write 0ns
r01ds0062ej0120 rev.1.20 page 92 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v switching characteristics (v cc1 =v cc2 =3.0to3.6v, v ss =0v, and t a =t opr , unless otherwise noted) note: 1. the value is calculated using the formulas below based on the base clock cycles (t c(base) ) and respective cycles of tsu(a-r), tw(r), tsu(a-w), and tw(w) set by registers ebc0 to ebc3. if the calculation results in a negative value, modify the value to be set. for details on how to set values, refer to the user?s manual. t su(s-ale) = t su(a-ale) = t w(ale) = (tsu(a-r) - 0.5) t c(base) -15 [ns] t w(r) = tw(r) t c(base) -10 [ns] t w(w) = t su(d-w) = tw(w) t c(base) -10 [ns] table 5.58 external bus timing (multiplexed bus) symbol characteristic measurement condition value unit min. max. t su(s-ale) chip-select setup time before ale refer to figure 5.6 (1) ns t h(r-s) chip-select hold time after read 1.5 t c(base) - 10 ns t su(a-ale) address setup time before ale (1) ns t h(ale-a) address hold time after ale 0.5 t c(base) - 5 ns t h(r-a) address hold time after read 1.5 t c(base) - 10 ns t d(ale-r) ale-read delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w (ale) ale pulse width (1) ns t dis(r-a) address disable time after read 8ns t w(r) read pulse width (1) ns t h(w-s) chip-select hold time after write 1.5 t c(base) - 10 ns t h(w-a) address hold time after write 1.5 t c(base) - 10 ns t d(ale-w) ale-write delay time 0.5 t c(base) - 5 0.5 t c(base) + 10 ns t w(w) write pulse width (1) ns t su(d-w) data setup time before write (1) ns t h(w-d) data hold time after write 0.5 t c(base) ns
r01ds0062ej0120 rev.1.20 page 93 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics v cc1 =v cc2 =3.3v switching characteristics (v cc1 =v cc2 =3.0to3.6v, v ss =0v, and t a =t opr , unless otherwise noted) table 5.59 serial interface symbol characteristic measurement condition value unit min. max. t d (c-q) txdi output delay time refer to figure 5.6 80 ns t h (c-q) txdi output hold time 0ns table 5.60 intelligent i/o symbol characteristic measurement condition value unit min. max. t d (isclk2-txd) istxd2 output delay time refer to figure 5.6 180 ns t h (isclk2-rxd) istxd2 output hold time 0ns
r01ds0062ej0120 rev.1.20 page 94 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics figure 5.6 switching characteri stic measurement circuit figure 5.7 external clock input timing 30 pf pin to be measured mcu xin t w(xh) t w(xl) t r(x) t f(x) t c(x)
r01ds0062ej0120 rev.1.20 page 95 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics figure 5.8 external bus timing for separate bus cs0 to cs3 a23 to a0, bc0 and bc1 rd d15 to d0 t h(r-d) t h(r-s) external bus timing (separate bus) read cycle t w(r) t su(s-r) t h(r-a) t su(a-r) write cycle cs0 to cs3 a23 to a0, bc0 and bc1 wr, wr0 and wr1 d15 to d0 t su(d-w) t h(w-d) t su(d-r) t h(w-s) t w(w) t su(s-w) t h(w-a) t su(a-w) measurement conditions criterion for input voltage criterion for output voltage v ih v il v oh v ol 2.5 v 0.8 v 2.0 v 0.8 v 1.5 v 0.5 v 2.4 v 0.5 v item v = v = 4.2 to 5.5 v cc1 cc2 v = v = 3.0 to 3.6 v cc1 cc2 t cr t cw
r01ds0062ej0120 rev.1.20 page 96 of 99 sep 26, 2011 r32c/111 group 5. electrical characteristics figure 5.9 external bus timing for multiplexed bus cs0 to cs3 a23 to a8, bc0 and bc1 rd d15 to d8 t h(r-d) t h(r-s) external bus timing (multiplexed bus) read cycle t w(r) t su(s-ale) t h(r-a) t su(a-ale) write cycle wr, wr0 and wr1 t su(d-r) measurement conditions ale t w(ale) address t su(a-ale) a15/d15 to a0/d0, bc0/d0 data t h(ale-a) t d(ale-r) t h(r-d) t su(d-r) cs0 to cs3 a23 to a8, bc0 and bc1 d15 to d8 t h(w-d) t h(w-s) t w(w) t su(s-ale) t h(w-a) t su(a-ale) t su(d-w) ale t w(ale) address t su(a-ale) a15/d15 to a0/d0, bc0/d0 data t h(ale-a) t d(ale-w) t h(w-d) t su(d-w) t dis(r-a) t dis(r-d) t cr t cw criterion for input voltage criterion for output voltage v ih v il v oh v ol 2.5 v 0.8 v 2.0 v 0.8 v 1.5 v 0.5 v 2.4 v 0.5 v item v = v = 4.2 to 5.5 v cc1 cc2 v = v = 3.0 to 3.6 v cc1 cc2
r01ds0062ej0120 rev.1.20 page 97 of 99 sep 26, 2011 r32c/111 group 5. ele ctrical characteristics figure 5.10 timing of peripheral functions taiin input taiout input t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) taiin input (in falling edge counting) taiout input (input for increment/ decrement switching) in event counter mode taiin input (in rising edge counting) t h(tin-up) tbiin input adtrg input t c(tb) t w(tbh) t w(tbl) t w(adl) clki t c(ck) t w(ckh) t w(ckl) txdi t d(c-q) t h(c-q) rxdi t su(d-c) t h(c-d) inti input t w(inl) t w(inh) nmi input two cpu clock cycles + 300 ns or more two cpu clock cycles + 300 ns or more t su(up-tin) t w(adh)
r01ds0062ej0120 rev.1.20 page 98 of 99 sep 26, 2011 r32c/111 group appendix 1. package dimensions appendix 1. package dimensions terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark x 125 26 50 51 75 76 100 f * 1 *3 * 2 z e z d e d h d h e b p detail f l 1 a 2 a 1 l a c l 1 z e z d c 1 b 1 b p a 1 h e h d y 0.08 e 0.5 c 0 8 x l 0.35 0.5 0.65 0.05 0.1 0.15 a 1.7 15.8 16.0 16.2 15.8 16.0 16.2 a 2 1.4 e 13.9 14.0 14.1 d 13.9 14.0 14.1 reference symbol dimension in millimeters min nom max 0.15 0.20 0.25 0.09 0.145 0.20 0.08 1.0 1.0 0.18 0.125 1.0 previous code jeita package code renesas code plqp0100kb-a 100p6q-a / fp-100u / fp-100uv mass[typ.] 0.6g p-lqfp100-14x14-0.50 e y s s 0.5 z e z d 0.5 0.29 0.25 0.21 b e b 1 y 0.10 0.5 x a 1.05 e 5.5 d 5.5 reference symbol dimension in millimeters min nom max 0.29 0.34 0.39 0.08 w 0.20 v 0.15 previous code jeita package code renesas code ptlg0100ka-a 100f0m mass[typ.] 0.1g p-tflga100-5.5x5.5-0.50 s wb s wa v (laser mark) index mark index mark s y s a e e b b 1 ms ab ms ab b 10 9 8 7 6 5 4 3 2 1 k j h g f e d c b a a z e z d e d 4
r01ds0062ej0120 rev.1.20 page 99 of 99 sep 26, 2011 r32c/111 group appendix 1. package dimensions detail f c a l 1 l a 1 a 2 index mark * 2 * 1 * 3 f 80 61 60 41 40 21 20 1 x z e z d e h e d h d e b p 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. previous code jeita package code renesas code plqp0080kb-a 80p6q-a mass[typ.] 0.5g p-lqfp80-12x12-0.50 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 12.1 12.0 11.9 d 12.1 12.0 11.9 e 1.4 a 2 14.2 14.0 13.8 14.2 14.0 13.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 10 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section c bp c 1 b 1 y s s terminal cross section b 1 c 1 b p c 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. index mark * 3 17 32 64 49 116 33 48 f * 1 * 2 x b p h e e h d d z d z e detail f a c a 2 a 1 l 1 l p-lqfp64-10x10-0.50 0.3g mass[typ.] 64p6q-a / fp-64k / fp-64kv plqp0064kb-a renesas code jeita package code previous code 1.0 0.125 0.18 1.25 1.25 0.08 0.20 0.145 0.09 0.25 0.20 0.15 max nom min dimension in millimeters symbol reference 10.1 10.0 9.9 d 10.1 10.0 9.9 e 1.4 a 2 12.2 12.0 11.8 12.2 12.0 11.8 1.7 a 0.15 0.1 0.05 0.65 0.5 0.35 l x 8 0 c 0.5 e 0.08 y h d h e a 1 b p b 1 c 1 z d z e l 1 e y s s
a- 1 revision history r32c/111 group datasheet rev. date description page summary 0.03 oct 17, 2007 ? initial release 0.30 aug 19, 2008 ? second edition released ? the manual in general ? maximum operating frequency changed from 48 mhz to 50 mhz ? specification of on-c hip oscillator disclosed ? microprocessor mode becomes optional ? ?memory-expanded mode? changed to ?memory expansion mode? chapter 1 1 ? ?(mcus)? added to line 1 of 1.1 ? applications in 1.1.1 revised and modified ? ?attention users? below 1.1.1 modified to ?notes to users?; ?the specification? in this box changed to ?specifications? 2 ? ?instructions? in ?cpu? of table 1.1 deleted ? minimum instruction exec ution time in ?cpu? of table 1.1 changed ? microprocessor mode in cpu? of table 1.1 changed to optional ? ?tbd? for ?voltage detection? in table 1.1 deleted ? ?3 circuits? for ?clock? in table 1.1 changed to ?4 circuits? ? ?total interrupt vectors? in table 1.1 changed to ?interrupt vectors? ? trigger sources? for dma in table 1.1 modified to ?request sources?; request sources for ?dma? defined as 51 ? scribal error: ?perip heral interrupt sources? for ?dmacii? in table 1.1 corrected to ?peripheral interrupt source? 3 ? unit names in table 1.2 sorted in chapter order ? description for ?a /d converter? in table 1.2 changed ? ?operating frequency? in table 1.2 changed from ?48 mhz? to ?50 mhz? ? ?version n? and ?version d? added to ?operating temperature? in table 1.2 ; ?optional? deleted ? values for ?current consumption? in table 1.2 added 4 ? ?version n? and ?version d? added to table 1.3 ? all ?version n?s in table 1.3 become on planning phase 6? figure 1.2 modified 7 ? note 2 for figure 1.3 modified 8 ? scribal error: ?clk5/? (pin no. 21) in table 1.4 corrected to ?clk5? 11 ? description for ?connecting pins for decoupling ca pacitor?, ?cnvss?, and ?debug port? in table 1.7 modified 12 ? some descriptions for ? wr0 / wr1 / wr / bc0 / bc1 / rd ? of ?bus control pins? in table 1.8 modified 13, 14 ? functional category items in tables 1.9 and 1.10 sorted in chapter order; descriptions modified chapter 2 ? ? descriptions for this chapter mo dified; expression ?dmac-related registers?s modified to ?d mac-associated registers?s 15 ? ?data register? and ?address register? in figure 2.1 pluralized; explanation in notes 1 and 2 for this figure revised
a- 2 15, 16 ? ?interrupt table register? in figure 2.1 and 2.1.6 changed to ?interrupt vector table base register? 18 ? scribal error: ?24 bit? in 2.2.2 corrected to ?32 bit? chapter 3 19 ? descriptions for this chapter and figure 3.1 modified chapter 4 20 ? ?(sfr)? of chapter title changed to ?(sfrs)? ? description for in itial paragraph of chapter 4 modified ? reset value for ccr and pbc in table 4.1 changed 21, 22 ? ?uarti bus collision detection inte rrupt control register? (i = 0 to 6) in tables 4.2 and 4.3 changed to ?uarti bu s collision, start/stop condition detection interrupt control register? ? ?dmai interrupt? in tables 4.2 and 4.3 changed to ?dmai transfer complete interrupt? 22 ? reset value for iio3ir and iio8ir to iio11r in table 4.3 modified 25 ? scribal error: address ?00010fh? added to table 4.6 32 ? ?upward/downward counting select register? in table 4.13 changed to ?increment/decrement counting select register? 38 ? csop2 for address 040056h in table 4.19 deleted ? reset value for cm3 in table 4.19 changed 43 ? ?dmai source select register i? in table 4.24 changed to ?dmai request source select register i? chapter 5 ? ? this chapter newly added appendix 1 81 ? ?package dimension? as title changed to ?package dimensions? 1.10 sep 17, 2009 ? third edition released ? the manual in general ? added 100-pin plastic molded lga and 80- and 64-pin plastic molded lqfp packages ? when new tables/figures are added for 80-/64-pin packages, add the following description: ?(for the 100-pin package)? to the title of corresponding curr ent tables/figures chapter 1. overview 1 ? added description for 100-pin lga and 80-/64-pin pack ages to lines 12 and 13 of 1.1 ; added description ?a maximum of? to ?nine channels of serial interface?; deleted the wh ole description of ?notes to users? 2 ? changed minimum ram size ?40? in table 1.1 , to ?32? ? modified description for ?e xternal bus expansion?, to table 1.1 ; moved this unit be low ?clock? 3 ? added ?(optional)? for iebus mode for ?inte lligent i/o? in table 1.2 ? modified description for ?flash memory? in tables 1.2 ? added ?100-pin plastic molded tflga (ptlg0100ka-a)? to table 1.2 4-7 ? added tables 1.3 to 1.6 to provide specificat ions for 80-/64-pin packages revision history r32c/111 group datasheet rev. date description page summary
a- 3 8 ? completed ?under developmen t? phase of part numbers r5f64110dfb, r5f64111dfb, r5f64112dfb, r5f64114dfb, r5f64115dfb, and r5f64116dfb in table 1.7 ? added product information for 100-pin lga and 80-/64-pin packages to table 1.7 9 ? added product information for 100-pin lga and 80-/64-pin packages, and 32-kbyte ram to figure 1.1 ? deleted hyphenation for part number in figure 1.1 11, 12, 14, 18, 21 ? added figures 1.3, 1.4, and 1.6 to 1.8 to provide block diagrams and pin assignment for 100-pin lga and 80-/64-pin packages 13 ? changed the order of notes in figures 1.5 15-17 ? added pin no. for 100-pin lga package to tables 1.8 to 1.10 19, 20, 22, 23 ? added tables 1.11 to 1.14 to provide pin charac teristics for 80-/64-pin packages. 24 ? changed the following expression: ?a ceramic resonator or a crystal oscillator? for ?main cl ock input/output? in table 1.15 , to ?a crystal, or a ceramic resonator? 25 ? modified descriptions for hlda and rdy of ?bus control pins? in table 1.16 26 ? changed the following expression: ?selected? for ?input port? in table 1.17 , to ?selectable? ? modified description ?txd2? for txd0 to txd8 of ?serial interface? in table 1.17 , to ?txd2 output? 28-30 ? added tables 1.19 to 1.21 to provide pin definitions and functions for 80-/64-pin packages chapter 2. cpu ? ? made major text modifica tions to this chapter 33 ? changed the following expression: ?a requested inte rrupt?s priority level? in line 2 of 2.1.8.11 , to ?the interr upt request level? chapter 3. memory 35 ? made major text modifications to this chapter ? changed ram size ?40? in line 7 of this chapter, to ?63?, and address ?0000a3ffh? in line 8, to ?0000ffffh? ? added descriptions for 32-kbyte ram and 128-kbyte rom to figure 3.1 ? changed two ?can be?s in notes 3 and 4 of figure 3.1 , to ?becomes?s chapter 4. sfrs 36 ? changed hexadecimal format of reset values for registers ccr and fmcr in table 4.1 , to binary ? added febc3 register to addresses 000010h-000011h in table 4.1 ? changed febc register for addresses 00001ch-00001dh, to febc0 in table 4.1 ? modified the following register name in table 4.1 : ?chip-select boundary (between n and n + 1) setting register?, to ?chip-select n and n + 1 boundary setting register? revision history r32c/111 group datasheet rev. date description page summary
a- 4 37, 38 ? changed register names associated with ?start/stop condition? for bcniic in tables 4.2 and 4.3 , to ?start condition/stop condition? 45 ? modified reset values ?xxxx xxxxb ? and ?xxxx 000xb? for registers u7rb and u8rb in table 4.10 , to ?xxxxh? 46 ? changed expression of register name ?xi register yi register? (i = 0 to 15) and register symbol ?xir, yir? in table 4.11 , to ?xi register/yi register? and ?xir/yir?, respectively 51 ? changed hexadecimal format of reset values for pdi in table 4.16 , to binary 54 ? modified note 1 in table 4.19 55 ? merged addresses 40090h to 40093h in table 4.20 , into previous page ? modified reset values for ifs0 and ifs2 in table 4.20 ; added notes 1 to 3 for 80-/64-pin packages and ifs7 register 55-57 ? modified the following register name in tables 4.20 to 4.22 : ?port pi_j port function select register?, to ?port pi_j function select register? 59 ? modified register name ?dmai requ est source select register 1? in table 4.24 , to ?dmai request source select register? ? changed register names ?wake-up interrupt priority level control register 2? and ?wake-up interrupt prio rity level control register 1? in table 4.24 , to ?wake-up ipl setting register 2? and ?wake-up ipl setting register 1?, respectively chapter 5. electrical characteristics 60 ? added notes 2 and 3 for 80-/64-pin packages to table 5.1 61 ? added specification of ?dv cc1 /dt? to table 5.2 ; added notes 2, 4, and 5 for 80-/64-pin packages 62 ? added note 2 for table 5.3 63 ? added note 3 for 80-/64-pin packages to table 5.4 65 ? modified description ?v cc ?s in table 5.6 , to ?v cc1 ?s and ?v cc2 ?s 66 ? added table 5.7 to provide ram electrical characteristics ? deleted specification of ?t ps ? from table 5.8 67 ? deleted measurement condition for power supply circuit timing characteristics in table 5.9 ? added ?supply voltage for internal logic? to figure 5.3 and deleted ?cpu clock? from the figure ? changed voltage condition for table 5.11 , from ?v cc1 = v cc2 = 3.3 to 5.5 v? to ?v cc1 = v cc2 = 4.2 to 5.5 v?; clarified maximum value for ? vdet? in table 5.11 ; modified self-consuming current ?v cc ?, to ?v cc1 ? 68 ? changed typical value and maximum value for f so(pll) in table 5.12 , to ?55? and ?80? respectively ? changed the following expression s: ?pll frequency synthesizer stabilization time? in table 5.12 , to ?pll lock time? and ?t osc(pll) ?, to ?t lock(pll) ? ? modified description for note1 of table 5.13 revision history r32c/111 group datasheet rev. date description page summary
a- 5 70, 82 ? added notes 1 and 2 for 80-/64-pin packages to tables 5.15 and 5.38 71, 83 ? deleted ports p7_0, p7_1, and p8_5 for r pullup from tables 5.16 and 5.39 ; added notes 1 and 2 for 80-/64-pin packages 72, 84 ? added ?xin? as ?active? to first, third, and sixth rows of tables 5.17 and 5.40 ? deleted specification of icc under condition ?ta = 85c ? from tables 5.17 and 5.40 73, 85 ? modified minimum value ?0.125? for ad in tables 5.18 and 5.41 , to ?0.25?; added note 1 for 80-/64-pin packages 75, 87 ? clarified three ?tbd?s for external bus timing in tables 5.21 and 5.44 78 ? corrected a typo ?t h(c-q) ? in table 5.30 , to ?t h(c-d) ? 78, 90 ? modified maximum value for t h(c-d) ?30? in tables 5.30 and 5.53 , to ?80? ? modified minimum value for t w(adh) in tables 5.31 and 5.54 , to ? ? ? added tables 5.33 and 5.56 to provide intelligent i/o timing requirements 79, 91 ? changed the third formula of note 1 in tables 5.34 and 5.57 80, 92 ? modified minimum value of t h(w-d) ?0? in tables 5.35 and 5.58 , to ?0.5 x t c(base) ?; changed the first formula of note 1 81, 93 ? modified ?characteristic? for t h(c-q) in tables 5.36 and 5.59 , from ?txdi hold time? to ?txdi output hold time? ? added tables 5.37 and 5.60 to provide inte lligent switching characteristics 83 ? changed measurement condition fo r ?high level input current? in table 5.39 , from ?v i = 3 v? to ?v i = 3.3 v? 85 ? added a skipped word ?error? after ?differential non-linearity? in table 5.41 87 ? corrected typos ?t w(h) ,? ?t w(l) ?, ?t r ?, and ?t f ? in table 5.43 , to ?t w(xh) ?, ?t w(xl) ?, ?t r(x) ?, and ?t f(x) ?, respectively 95 ? changed d15 to d0 output period of write cycle in figures 5.8 96 ? changed d15 to d8 output period of write cycle in figures 5.9 appendix 1 98, 99 ? added figures for 100-pin plasti c molded lga, and 80-/64-pin plastic molded lqfp packages 1.20 sep 26, 2011 ? fourth edition released ? the manual in general ? applied new renesas templates and formats to the manual ? changed company name to ?renesas electronics corporation? and changed related descriptions due to business merger of renesas technology corporation and nec electronics corporation ? modified expressions ?version n? and ?v ersion d? to ?n version? and ?d version?, respectively (under chapters 1 and 5) chapter 1. overview ? ? modified wording and enhanced description in this chapter revision history r32c/111 group datasheet rev. date description page summary 3 ad --------- -
a- 6 2, 4, 6 ? modified the following expressions in tables 1.1, 1.3, and 1.5 : ?main clock oscillator stop/re-o scillation detection? to ?main clock oscillator stop/restart detection?, and ?inputs/outputs? to ?i/o ports? 3 ? deleted note 1 from table 1.2 4, 6 ? deleted memory expansion mode and microprocessor mode from the operating mode of the cpu in tables 1.3 and 1.5 5, 7 ? deleted note 2 from tables 1.4 and 1.6 7 ? corrected package code in table 1.6 to ?plqp0064kb-a? 8 ? completed ?under development? phase of r5f6411edfn in table 1.7 10-12 ? deleted note 1 from figures 1.2 to 1.4 13 ? corrected a typo ?r5_3? for pin number 41 in figure 1.5 to ?p5_3? 13, 18, 21 ? changed order of signals in figures 1.5, 1.7, and 1.8 15, 19, 22 ? changed order of timer pins ?tb5in/ta0in? in tables 1.8, 1.11, and 1.13 to ?ta0in/tb5in? 24 ? modified expression ?fc? in table 1.15 to ?low speed clocks? chapter 2. cpu ? ? modified wording and enhanced description in this chapter 32 ? corrected a typo ?r3r0? in line 3 of 2.1.1 to ?r3r1? chapter 3. memory ? ? modified wording and enhanced description in this chapter chapter 4. sfrs ? ? modified wording and enhanced description in this chapter 41, 42, 44 ? changed hexadecimal format of re set values for re gisters g1bcr0, g2bcr0, and g0bcr0 in tables 4.6, 4.7, and 4.9 to binary 41, 44 ? changed register name ?group i timer measurement prescaler register? in tables 4.6 and 4.9 to ?group i time measurement prescaler register? 43 ? modified expression ?ie bus? in table 4.8 to ?iebus? 46 ? modified expression ?xy control register? in table 4.11 to ?x-y control register? 48 ? changed register name ?uart2 transmission/receive mode register? and ?increment/decrement counting select register? in table 4.13 to ?uart2 transmit/receive mode register? and ?increment/decrement select regi ster?, respectively; changed hexadecimal format of reset valu es for registers tabsr, onsf, and trgsr to binary 50 ? changed reset value ?x00x x000b? for ad0con2 register in table 4.15 to ?xx0x x000b? 59 ? changed register name ?external inte rrupt source select register i? in table 4.24 to ?external interrupt reque st source select register i? chapter 5. electrical characteristics ? ? modified wording and enhanced description in this chapter ? changed expression ?clock pe riod? to ?clock cycle time? 61 ? changed format for ports p0 and p1 in table 5.2 revision history r32c/111 group datasheet rev. date description page summary
a- 7 66 ? chaged expression ?programmi ng and erasure endurance? in table 5.8 to ?program and erase cycles?; changed its unit ?times? in the table and note 1 to ?cycles? 68 ? changed order of descriptions of ?t rec(stop) ? and ?t rec(wait) ? in table 5.13 and figure 5.4 69 ? changed expressions ? cs0 ? and ?a23 to a0, bc0 to bc3 ? in figure 5.5 to ?chip select? and ?address?, respectively 78, 90 ? corrected ?inti? in title of tables 5.32 and 5.55 to ? inti ? 81, 93 ? added measurement condition to tables 5.37 and 5.60 appendix 1. package dimensions 98-99 ? added a seating plane to the drawing of package dimension all trademarks and registered trademarks are the property of their respective owners. revision history r32c/111 group datasheet rev. date description page summary
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manu al. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the bod y of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are general ly in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through cu rrent flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a pr oduct that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the po ssible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during pr ogram execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset li ne is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different part number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different part numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different part numbe rs, implement a system-evaluation test for each of the products.
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is s ubject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also , please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control l aws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose rela ting to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporate d into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", an d "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics produ ct before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. fu rther, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended wh ere you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electroni cs data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment ; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or syst ems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct thr eat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas el ectronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have s pecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design . please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compati bility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this doc ument or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2011 renesas electronics corporation. all rights reserved. colophon 1.1

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